ef8655adc8
CUDA-12 no longer supports 32-bit compilation. Tests agnostic to 32/64 compilation mode are switched to use nvptx64. Tests that do care about it have 32-bit ptxas compilation disabled with cuda-12+. Differential Revision: https://reviews.llvm.org/D152199
37 lines
973 B
LLVM
37 lines
973 B
LLVM
; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s
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; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_20 | %ptxas-verify %}
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declare i1 @llvm.nvvm.isspacep.const(ptr) readnone noinline
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declare i1 @llvm.nvvm.isspacep.global(ptr) readnone noinline
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declare i1 @llvm.nvvm.isspacep.local(ptr) readnone noinline
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declare i1 @llvm.nvvm.isspacep.shared(ptr) readnone noinline
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; CHECK: is_const
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define i1 @is_const(ptr %addr) {
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; CHECK: isspacep.const
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%v = tail call i1 @llvm.nvvm.isspacep.const(ptr %addr)
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ret i1 %v
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}
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; CHECK: is_global
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define i1 @is_global(ptr %addr) {
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; CHECK: isspacep.global
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%v = tail call i1 @llvm.nvvm.isspacep.global(ptr %addr)
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ret i1 %v
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}
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; CHECK: is_local
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define i1 @is_local(ptr %addr) {
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; CHECK: isspacep.local
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%v = tail call i1 @llvm.nvvm.isspacep.local(ptr %addr)
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ret i1 %v
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}
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; CHECK: is_shared
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define i1 @is_shared(ptr %addr) {
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; CHECK: isspacep.shared
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%v = tail call i1 @llvm.nvvm.isspacep.shared(ptr %addr)
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ret i1 %v
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}
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