ef8655adc8
CUDA-12 no longer supports 32-bit compilation. Tests agnostic to 32/64 compilation mode are switched to use nvptx64. Tests that do care about it have 32-bit ptxas compilation disabled with cuda-12+. Differential Revision: https://reviews.llvm.org/D152199
66 lines
1.7 KiB
LLVM
66 lines
1.7 KiB
LLVM
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s --check-prefix=PTX32
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; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s --check-prefix=PTX64
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; RUN: %if ptxas && !ptxas-12.0 %{ llc < %s -march=nvptx -mcpu=sm_20 | %ptxas-verify %}
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; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_20 | %ptxas-verify %}
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;; i8
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define i8 @ld_global_i8(ptr addrspace(0) %ptr) {
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; PTX32: ld.u8 %r{{[0-9]+}}, [%r{{[0-9]+}}]
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; PTX32: ret
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; PTX64: ld.u8 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
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; PTX64: ret
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%a = load i8, ptr addrspace(0) %ptr
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ret i8 %a
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}
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;; i16
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define i16 @ld_global_i16(ptr addrspace(0) %ptr) {
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; PTX32: ld.u16 %r{{[0-9]+}}, [%r{{[0-9]+}}]
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; PTX32: ret
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; PTX64: ld.u16 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
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; PTX64: ret
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%a = load i16, ptr addrspace(0) %ptr
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ret i16 %a
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}
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;; i32
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define i32 @ld_global_i32(ptr addrspace(0) %ptr) {
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; PTX32: ld.u32 %r{{[0-9]+}}, [%r{{[0-9]+}}]
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; PTX32: ret
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; PTX64: ld.u32 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
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; PTX64: ret
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%a = load i32, ptr addrspace(0) %ptr
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ret i32 %a
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}
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;; i64
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define i64 @ld_global_i64(ptr addrspace(0) %ptr) {
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; PTX32: ld.u64 %rd{{[0-9]+}}, [%r{{[0-9]+}}]
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; PTX32: ret
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; PTX64: ld.u64 %rd{{[0-9]+}}, [%rd{{[0-9]+}}]
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; PTX64: ret
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%a = load i64, ptr addrspace(0) %ptr
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ret i64 %a
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}
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;; f32
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define float @ld_global_f32(ptr addrspace(0) %ptr) {
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; PTX32: ld.f32 %f{{[0-9]+}}, [%r{{[0-9]+}}]
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; PTX32: ret
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; PTX64: ld.f32 %f{{[0-9]+}}, [%rd{{[0-9]+}}]
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; PTX64: ret
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%a = load float, ptr addrspace(0) %ptr
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ret float %a
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}
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;; f64
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define double @ld_global_f64(ptr addrspace(0) %ptr) {
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; PTX32: ld.f64 %fd{{[0-9]+}}, [%r{{[0-9]+}}]
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; PTX32: ret
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; PTX64: ld.f64 %fd{{[0-9]+}}, [%rd{{[0-9]+}}]
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; PTX64: ret
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%a = load double, ptr addrspace(0) %ptr
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ret double %a
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}
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