ef8655adc8
CUDA-12 no longer supports 32-bit compilation. Tests agnostic to 32/64 compilation mode are switched to use nvptx64. Tests that do care about it have 32-bit ptxas compilation disabled with cuda-12+. Differential Revision: https://reviews.llvm.org/D152199
31 lines
1.1 KiB
LLVM
31 lines
1.1 KiB
LLVM
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
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; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s
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; RUN: %if ptxas && !ptxas-12.0 %{ llc < %s -march=nvptx -mcpu=sm_20 | %ptxas-verify -m32 %}
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; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_20 | %ptxas-verify %}
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; This test makes sure that the result of vector compares are properly
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; scalarized. If codegen fails, then the type legalizer incorrectly
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; tried to promote <2 x i1> to <2 x i8> and instruction selection failed.
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; CHECK-LABEL: .visible .func foo(
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define void @foo(ptr %a, ptr %b, ptr %r1, ptr %r2) {
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; CHECK: ld.v2.u32
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%aval = load <2 x i32>, ptr %a
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; CHECK: ld.v2.u32
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%bval = load <2 x i32>, ptr %b
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; CHECK: setp.lt.s32
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; CHECK: setp.lt.s32
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%res = icmp slt <2 x i32> %aval, %bval
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%t1 = extractelement <2 x i1> %res, i32 0
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%t2 = extractelement <2 x i1> %res, i32 1
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; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0
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; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0
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%t1a = zext i1 %t1 to i32
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%t2a = zext i1 %t2 to i32
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; CHECK: st.u32
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; CHECK: st.u32
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store i32 %t1a, ptr %r1
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store i32 %t2a, ptr %r2
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ret void
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}
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