ef8655adc8
CUDA-12 no longer supports 32-bit compilation. Tests agnostic to 32/64 compilation mode are switched to use nvptx64. Tests that do care about it have 32-bit ptxas compilation disabled with cuda-12+. Differential Revision: https://reviews.llvm.org/D152199
28 lines
1.0 KiB
LLVM
28 lines
1.0 KiB
LLVM
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
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; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s
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; RUN: %if ptxas && !ptxas-12.0 %{ llc < %s -march=nvptx -mcpu=sm_20 | %ptxas-verify %}
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; RUN: %if ptxas %{llc < %s -march=nvptx64 -mcpu=sm_20 | %ptxas-verify %}
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; This test makes sure that vector selects are scalarized by the type legalizer.
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; If not, type legalization will fail.
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; CHECK-LABEL: .visible .func foo(
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define void @foo(ptr addrspace(1) %def_a, ptr addrspace(1) %def_b, ptr addrspace(1) %def_c) {
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entry:
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; CHECK: ld.global.v2.u32
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; CHECK: ld.global.v2.u32
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; CHECK: ld.global.v2.u32
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%tmp4 = load <2 x i32>, ptr addrspace(1) %def_a
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%tmp6 = load <2 x i32>, ptr addrspace(1) %def_c
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%tmp8 = load <2 x i32>, ptr addrspace(1) %def_b
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; CHECK: setp.gt.s32
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; CHECK: setp.gt.s32
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%0 = icmp sge <2 x i32> %tmp4, zeroinitializer
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; CHECK: selp.b32
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; CHECK: selp.b32
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%cond = select <2 x i1> %0, <2 x i32> %tmp6, <2 x i32> %tmp8
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; CHECK: st.global.v2.u32
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store <2 x i32> %cond, ptr addrspace(1) %def_c
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ret void
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}
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