3508f12335
This patch adds the initial support for vector functions and register banks within GlobalISel. With this patch, we are able to support simple functions that return vectors, and also functions that perform simple operations. This patch also: - Legalizes vector types for G_AND, G_OR, G_XOR, G_ADD, G_SUB, G_BITCAST, G_FADD, G_FSUB - Introduce initial support for bitcasting (that will need to be extended upon) - Add various different test cases to for test vector support within GlobalISel Differential Revision: https://reviews.llvm.org/D137785
76 lines
2.0 KiB
LLVM
76 lines
2.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -ppc-vsr-nums-as-vr \
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; RUN: -ppc-asm-full-reg-names -global-isel -o - < %s | FileCheck %s
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define <16 x i8> @test_add_v16i8(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: test_add_v16i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vaddubm v2, v2, v3
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; CHECK-NEXT: blr
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%res = add <16 x i8> %a, %b
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ret <16 x i8> %res
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}
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define <8 x i16> @test_add_v8i16(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: test_add_v8i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vadduhm v2, v2, v3
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; CHECK-NEXT: blr
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%res = add <8 x i16> %a, %b
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ret <8 x i16> %res
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}
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define <4 x i32> @test_add_v4i32(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test_add_v4i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vadduwm v2, v2, v3
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; CHECK-NEXT: blr
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%res = add <4 x i32> %a, %b
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ret <4 x i32> %res
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}
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define <2 x i64> @test_add_v2i64(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_add_v2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vaddudm v2, v2, v3
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; CHECK-NEXT: blr
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%res = add <2 x i64> %a, %b
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ret <2 x i64> %res
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}
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define <16 x i8> @test_sub_v16i8(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: test_sub_v16i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsububm v2, v2, v3
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; CHECK-NEXT: blr
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%res = sub <16 x i8> %a, %b
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ret <16 x i8> %res
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}
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define <8 x i16> @test_sub_v8i16(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: test_sub_v8i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsubuhm v2, v2, v3
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; CHECK-NEXT: blr
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%res = sub <8 x i16> %a, %b
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ret <8 x i16> %res
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}
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define <4 x i32> @test_sub_v4i32(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test_sub_v4i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsubuwm v2, v2, v3
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; CHECK-NEXT: blr
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%res = sub <4 x i32> %a, %b
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ret <4 x i32> %res
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}
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define <2 x i64> @test_sub_v2i64(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_sub_v2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsubudm v2, v2, v3
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; CHECK-NEXT: blr
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%res = sub <2 x i64> %a, %b
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ret <2 x i64> %res
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}
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