ff23856c1c
This is a generic DAG combine version of D151055 which recognizes when a signed ABDS can be safely replaced with a unsigned ABDU instruction if it is legal. Alive2: https://alive2.llvm.org/ce/z/pb5BjG Differential Revision: https://reviews.llvm.org/D153328
40 lines
1.4 KiB
LLVM
40 lines
1.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le -mcpu=pwr9 < %s | FileCheck %s
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define <12 x i8> @zext_abdu(<12 x i8> %a, <12 x i8> %b) {
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; CHECK-LABEL: zext_abdu:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis 3, 2, .LCPI0_0@toc@ha
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; CHECK-NEXT: xxlxor 36, 36, 36
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; CHECK-NEXT: addi 3, 3, .LCPI0_0@toc@l
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; CHECK-NEXT: lxv 37, 0(3)
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; CHECK-NEXT: addis 3, 2, .LCPI0_1@toc@ha
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; CHECK-NEXT: addi 3, 3, .LCPI0_1@toc@l
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; CHECK-NEXT: lxv 33, 0(3)
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; CHECK-NEXT: addis 3, 2, .LCPI0_2@toc@ha
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; CHECK-NEXT: vperm 0, 4, 2, 5
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; CHECK-NEXT: vperm 5, 4, 3, 5
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; CHECK-NEXT: addi 3, 3, .LCPI0_2@toc@l
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; CHECK-NEXT: lxv 39, 0(3)
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; CHECK-NEXT: vperm 6, 4, 2, 1
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; CHECK-NEXT: vperm 1, 4, 3, 1
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; CHECK-NEXT: vperm 2, 4, 2, 7
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; CHECK-NEXT: vperm 3, 4, 3, 7
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; CHECK-NEXT: vabsduw 4, 5, 0
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; CHECK-NEXT: vabsduw 2, 3, 2
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; CHECK-NEXT: vabsduw 3, 1, 6
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; CHECK-NEXT: vpkuwum 3, 4, 3
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; CHECK-NEXT: vpkuwum 2, 2, 2
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; CHECK-NEXT: vpkuhum 2, 2, 3
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; CHECK-NEXT: blr
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entry:
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%aa = zext <12 x i8> %a to <12 x i32>
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%bb = zext <12 x i8> %b to <12 x i32>
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%s = sub nsw <12 x i32> %aa, %bb
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%c = icmp slt <12 x i32> %s, zeroinitializer
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%ss = sub nsw <12 x i32> zeroinitializer, %s
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%sel = select <12 x i1> %c, <12 x i32> %ss, <12 x i32> %s
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%ret = trunc <12 x i32> %sel to <12 x i8>
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ret <12 x i8> %ret
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}
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