a7bbcc4690
Scalable vector types from LLVM IR can be lowered to scalable vector types in MIR according to the RISCVAssignFn.
45 lines
1.5 KiB
LLVM
45 lines
1.5 KiB
LLVM
; RUN: llc -mtriple=riscv64 -mattr='+v' -O0 -global-isel -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o %t.out 2> %t.err
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; RUN: FileCheck %s --check-prefix=FALLBACK-WITH-REPORT-OUT < %t.out
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; RUN: FileCheck %s --check-prefix=FALLBACK-WITH-REPORT-ERR < %t.err
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declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(
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<vscale x 1 x i8>,
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<vscale x 1 x i8>,
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<vscale x 1 x i8>,
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i64)
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; FALLBACK_WITH_REPORT_ERR: <unknown>:0:0: unable to translate instruction: call:
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; FALLBACK-WITH-REPORT-OUT-LABEL: scalable_arg
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define <vscale x 1 x i8> @scalable_arg(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
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entry:
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%a = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(
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<vscale x 1 x i8> undef,
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<vscale x 1 x i8> %0,
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<vscale x 1 x i8> %1,
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i64 %2)
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ret <vscale x 1 x i8> %a
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}
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; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to translate instruction: call:
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; FALLBACK-WITH-REPORT-OUT-LABEL: scalable_inst
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define <vscale x 1 x i8> @scalable_inst(i64 %0) nounwind {
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entry:
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%a = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(
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<vscale x 1 x i8> undef,
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<vscale x 1 x i8> undef,
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<vscale x 1 x i8> undef,
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i64 %0)
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ret <vscale x 1 x i8> %a
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}
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; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to translate instruction: alloca:
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; FALLBACK-WITH-REPORT-OUT-LABEL: scalable_alloca
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define void @scalable_alloca() #1 {
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%local0 = alloca <vscale x 16 x i8>
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load volatile <vscale x 16 x i8>, ptr %local0
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ret void
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}
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