86eff6be68
This change adjusts the cost modeling used when the target does not have a schedule model with individual instruction latencies. After this change, we use the default latency information available from TargetSchedule. The default latency information essentially ends up treating most instructions as latency 1, with a few "expensive" ones getting a higher cost. Previously, we unconditionally applied the first legal pattern - without any consideration of profitability. As a result, this change both prevents some patterns being applied, and changes which patterns are exercised. (i.e. previously the first pattern was applied, afterwards, maybe the second one is because the first wasn't profitable.) The motivation here is two fold. First, this brings the default behavior in line with the behavior when -mcpu or -mtune is specified. This improves test coverage, and generally makes it less likely we will have bad surprises when providing more information to the compiler. Second, this enables some reassociation for ILP by default. Despite being unconditionally enabled, the prior code tended to "reassociate" repeatedly through an entire chain and simply moving the first operand to the end. The result was still a serial chain, just a different one. With this change, one of the intermediate transforms is unprofitable and we end up with a partially flattened tree. Note that the resulting code diffs show significant room for improvement in the basic algorithm. I am intentionally excluding those from this patch. For the test diffs, I don't seen any concerning regressions. I took a fairly close look at the RISCV ones, but only skimmed the x86 (particularly vector x86) changes. Differential Revision: https://reviews.llvm.org/D141017
81 lines
2.8 KiB
LLVM
81 lines
2.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RISCV32
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; Test ADDCARRY node expansion on a target that does not currently support ADDCARRY.
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; Signed fixed point multiplication eventually expands down to an ADDCARRY.
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declare i64 @llvm.smul.fix.i64 (i64, i64, i32)
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declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32)
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define i64 @addcarry(i64 %x, i64 %y) nounwind {
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; RISCV32-LABEL: addcarry:
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; RISCV32: # %bb.0:
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; RISCV32-NEXT: mul a4, a0, a3
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; RISCV32-NEXT: mulhu a5, a0, a2
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; RISCV32-NEXT: add a6, a5, a4
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; RISCV32-NEXT: mul a4, a1, a2
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; RISCV32-NEXT: add a4, a6, a4
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; RISCV32-NEXT: sltu a7, a4, a6
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; RISCV32-NEXT: sltu a5, a6, a5
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; RISCV32-NEXT: mulhu a6, a0, a3
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; RISCV32-NEXT: mulhu t0, a1, a2
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; RISCV32-NEXT: add a6, a6, t0
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; RISCV32-NEXT: add a5, a6, a5
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; RISCV32-NEXT: add a5, a5, a7
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; RISCV32-NEXT: mul a6, a1, a3
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; RISCV32-NEXT: add a5, a5, a6
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; RISCV32-NEXT: bgez a1, .LBB0_2
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; RISCV32-NEXT: # %bb.1:
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; RISCV32-NEXT: sub a5, a5, a2
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; RISCV32-NEXT: .LBB0_2:
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; RISCV32-NEXT: bgez a3, .LBB0_4
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; RISCV32-NEXT: # %bb.3:
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; RISCV32-NEXT: sub a5, a5, a0
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; RISCV32-NEXT: .LBB0_4:
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; RISCV32-NEXT: slli a5, a5, 30
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; RISCV32-NEXT: srli a1, a4, 2
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; RISCV32-NEXT: or a1, a5, a1
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; RISCV32-NEXT: slli a4, a4, 30
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; RISCV32-NEXT: mul a0, a0, a2
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; RISCV32-NEXT: srli a0, a0, 2
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; RISCV32-NEXT: or a0, a4, a0
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; RISCV32-NEXT: ret
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%tmp = call i64 @llvm.smul.fix.i64(i64 %x, i64 %y, i32 2);
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ret i64 %tmp;
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}
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; negative test for combineCarryDiamond(): ADDCARRY not legal
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define { i32, i32, i1 } @addcarry_2x32(i32 %x0, i32 %x1, i32 %y0, i32 %y1) nounwind {
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; RISCV32-LABEL: addcarry_2x32:
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; RISCV32: # %bb.0:
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; RISCV32-NEXT: add a3, a1, a3
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; RISCV32-NEXT: sltu a1, a3, a1
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; RISCV32-NEXT: add a4, a2, a4
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; RISCV32-NEXT: sltu a2, a4, a2
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; RISCV32-NEXT: add a1, a4, a1
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; RISCV32-NEXT: sltu a4, a1, a4
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; RISCV32-NEXT: or a2, a2, a4
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; RISCV32-NEXT: sw a3, 0(a0)
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; RISCV32-NEXT: sw a1, 4(a0)
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; RISCV32-NEXT: sb a2, 8(a0)
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; RISCV32-NEXT: ret
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%t0 = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %x0, i32 %y0)
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%s0 = extractvalue { i32, i1 } %t0, 0
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%k0 = extractvalue { i32, i1 } %t0, 1
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%t1 = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %x1, i32 %y1)
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%s1 = extractvalue { i32, i1 } %t1, 0
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%k1 = extractvalue { i32, i1 } %t1, 1
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%zk0 = zext i1 %k0 to i32
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%t2 = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %s1, i32 %zk0)
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%s2 = extractvalue { i32, i1 } %t2, 0
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%k2 = extractvalue { i32, i1 } %t2, 1
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%k = or i1 %k1, %k2
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%r0 = insertvalue { i32, i32, i1 } poison, i32 %s0, 0
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%r1 = insertvalue { i32, i32, i1 } %r0, i32 %s2, 1
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%r = insertvalue { i32, i32, i1 } %r1, i1 %k, 2
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ret { i32, i32, i1 } %r
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}
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