5b07059618
Table A.6 in the RISC-V ISA Manual indicates that sequentially
consistent atomic ops that have a matching instruction should be mapped
to `amo<op>.{w|d}.aqrl`. But sequentially consistent operations that are
mapped to lr/sc should produce `loop: lr.{w|d}.aqrl; <op>; sc.{w|d}.rl;
bnez loop`. Previously, LLVM produced an `sc.{w|d}.aqrl` which was
stronger than necessary. This patch adjusts the relevant logic so that a
`sc.{w|d}.rl` is produced.
Differential Revision: https://reviews.llvm.org/D146933
30 lines
1.1 KiB
LLVM
30 lines
1.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64IA %s
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; This test ensures that the output of the 'lr.w' instruction is sign-extended.
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; Previously, the default zero-extension was being used and 'cmp' parameter
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; higher bits were masked to zero for the comparison.
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define i1 @cmpxchg_i32_seq_cst_seq_cst(ptr %ptr, i32 signext %cmp,
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; RV64IA-LABEL: cmpxchg_i32_seq_cst_seq_cst:
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; RV64IA: # %bb.0: # %entry
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; RV64IA-NEXT: .LBB0_1: # %entry
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; RV64IA-NEXT: # =>This Inner Loop Header: Depth=1
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; RV64IA-NEXT: lr.w.aqrl a3, (a0)
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; RV64IA-NEXT: bne a3, a1, .LBB0_3
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; RV64IA-NEXT: # %bb.2: # %entry
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; RV64IA-NEXT: # in Loop: Header=BB0_1 Depth=1
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; RV64IA-NEXT: sc.w.rl a4, a2, (a0)
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; RV64IA-NEXT: bnez a4, .LBB0_1
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; RV64IA-NEXT: .LBB0_3: # %entry
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; RV64IA-NEXT: xor a1, a3, a1
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; RV64IA-NEXT: seqz a0, a1
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; RV64IA-NEXT: ret
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i32 signext %val) nounwind {
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entry:
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%0 = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst seq_cst
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%1 = extractvalue { i32, i1 } %0, 1
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ret i1 %1
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}
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