8a71f44e00
This doesn't bring us to parity with the test/CodeGen/RISCV/half-* test cases, it simply picks off an initial set that can be supported especially easy. In order to make the review more manageable, I'll follow up with other cases. There is zero innovation in the test cases - they simply take the existing half/float cases and replace f16->bf16 and half->bfloat. Differential Revision: https://reviews.llvm.org/D156895
27 lines
909 B
LLVM
27 lines
909 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin -verify-machineinstrs \
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; RUN: -target-abi ilp32f < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfbfmin -verify-machineinstrs \
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; RUN: -target-abi lp64f < %s | FileCheck %s
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define zeroext i1 @bfloat_is_nan(bfloat %a) nounwind {
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; CHECK-LABEL: bfloat_is_nan:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
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; CHECK-NEXT: feq.s a0, fa5, fa5
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; CHECK-NEXT: xori a0, a0, 1
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; CHECK-NEXT: ret
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%1 = fcmp uno bfloat %a, 0.000000e+00
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ret i1 %1
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}
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define zeroext i1 @bfloat_not_nan(bfloat %a) nounwind {
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; CHECK-LABEL: bfloat_not_nan:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
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; CHECK-NEXT: feq.s a0, fa5, fa5
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; CHECK-NEXT: ret
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%1 = fcmp ord bfloat %a, 0.000000e+00
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ret i1 %1
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}
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