3ac9fe69f7
This commit includes the necessary changes to clang and LLVM to support codegen of `RVE` and the `ilp32e`/`lp64e` ABIs. The differences between `RVE` and `RVI` are: * `RVE` reduces the integer register count to 16(x0-x16). * The ABI should be `ilp32e` for 32 bits and `lp64e` for 64 bits. `RVE` can be combined with all current standard extensions. The central changes in ilp32e/lp64e ABI, compared to ilp32/lp64 are: * Only 6 integer argument registers (rather than 8). * Only 2 callee-saved registers (rather than 12). * A Stack Alignment of 32bits (rather than 128bits). * ilp32e isn't compatible with D ISA extension. If `ilp32e` or `lp64` is used with an ISA that has any of the registers x16-x31 and f0-f31, then these registers are considered temporaries. To be compatible with the implementation of ilp32e in GCC, we don't use aligned registers to pass variadic arguments and set stack alignment\ to 4-bytes for types with length of 2*XLEN. FastCC is also supported on RVE, while GHC isn't since there is only one avaiable register. Differential Revision: https://reviews.llvm.org/D70401
214 lines
9.2 KiB
LLVM
214 lines
9.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -target-abi lp64e -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I-LP64E-FPELIM %s
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; RUN: llc -mtriple=riscv64 -target-abi lp64e -verify-machineinstrs -frame-pointer=all < %s \
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; RUN: | FileCheck -check-prefix=RV64I-LP64E-WITHFP %s
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; This file contains tests that will have differing output for the lp64e ABIs.
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define i64 @callee_float_in_regs(i64 %a, float %b) nounwind {
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; RV64I-LP64E-FPELIM-LABEL: callee_float_in_regs:
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; RV64I-LP64E-FPELIM: # %bb.0:
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; RV64I-LP64E-FPELIM-NEXT: addi sp, sp, -16
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; RV64I-LP64E-FPELIM-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-LP64E-FPELIM-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
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; RV64I-LP64E-FPELIM-NEXT: mv s0, a0
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; RV64I-LP64E-FPELIM-NEXT: sext.w a0, a1
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; RV64I-LP64E-FPELIM-NEXT: call __fixsfdi
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; RV64I-LP64E-FPELIM-NEXT: add a0, s0, a0
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; RV64I-LP64E-FPELIM-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-LP64E-FPELIM-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
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; RV64I-LP64E-FPELIM-NEXT: addi sp, sp, 16
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; RV64I-LP64E-FPELIM-NEXT: ret
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;
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; RV64I-LP64E-WITHFP-LABEL: callee_float_in_regs:
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; RV64I-LP64E-WITHFP: # %bb.0:
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; RV64I-LP64E-WITHFP-NEXT: addi sp, sp, -24
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; RV64I-LP64E-WITHFP-NEXT: sd ra, 16(sp) # 8-byte Folded Spill
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; RV64I-LP64E-WITHFP-NEXT: sd s0, 8(sp) # 8-byte Folded Spill
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; RV64I-LP64E-WITHFP-NEXT: sd s1, 0(sp) # 8-byte Folded Spill
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; RV64I-LP64E-WITHFP-NEXT: addi s0, sp, 24
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; RV64I-LP64E-WITHFP-NEXT: mv s1, a0
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; RV64I-LP64E-WITHFP-NEXT: sext.w a0, a1
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; RV64I-LP64E-WITHFP-NEXT: call __fixsfdi
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; RV64I-LP64E-WITHFP-NEXT: add a0, s1, a0
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; RV64I-LP64E-WITHFP-NEXT: ld ra, 16(sp) # 8-byte Folded Reload
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; RV64I-LP64E-WITHFP-NEXT: ld s0, 8(sp) # 8-byte Folded Reload
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; RV64I-LP64E-WITHFP-NEXT: ld s1, 0(sp) # 8-byte Folded Reload
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; RV64I-LP64E-WITHFP-NEXT: addi sp, sp, 24
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; RV64I-LP64E-WITHFP-NEXT: ret
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%b_fptosi = fptosi float %b to i64
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%1 = add i64 %a, %b_fptosi
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ret i64 %1
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}
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define i64 @caller_float_in_regs() nounwind {
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; RV64I-LP64E-FPELIM-LABEL: caller_float_in_regs:
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; RV64I-LP64E-FPELIM: # %bb.0:
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; RV64I-LP64E-FPELIM-NEXT: addi sp, sp, -8
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; RV64I-LP64E-FPELIM-NEXT: sd ra, 0(sp) # 8-byte Folded Spill
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; RV64I-LP64E-FPELIM-NEXT: li a0, 1
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; RV64I-LP64E-FPELIM-NEXT: lui a1, 262144
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; RV64I-LP64E-FPELIM-NEXT: call callee_float_in_regs
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; RV64I-LP64E-FPELIM-NEXT: ld ra, 0(sp) # 8-byte Folded Reload
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; RV64I-LP64E-FPELIM-NEXT: addi sp, sp, 8
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; RV64I-LP64E-FPELIM-NEXT: ret
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;
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; RV64I-LP64E-WITHFP-LABEL: caller_float_in_regs:
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; RV64I-LP64E-WITHFP: # %bb.0:
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; RV64I-LP64E-WITHFP-NEXT: addi sp, sp, -16
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; RV64I-LP64E-WITHFP-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-LP64E-WITHFP-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
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; RV64I-LP64E-WITHFP-NEXT: addi s0, sp, 16
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; RV64I-LP64E-WITHFP-NEXT: li a0, 1
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; RV64I-LP64E-WITHFP-NEXT: lui a1, 262144
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; RV64I-LP64E-WITHFP-NEXT: call callee_float_in_regs
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; RV64I-LP64E-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-LP64E-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
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; RV64I-LP64E-WITHFP-NEXT: addi sp, sp, 16
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; RV64I-LP64E-WITHFP-NEXT: ret
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%1 = call i64 @callee_float_in_regs(i64 1, float 2.0)
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ret i64 %1
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}
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define i64 @callee_float_on_stack(i128 %a, i128 %b, i128 %c, i128 %d, float %e) nounwind {
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; RV64I-LP64E-FPELIM-LABEL: callee_float_on_stack:
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; RV64I-LP64E-FPELIM: # %bb.0:
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; RV64I-LP64E-FPELIM-NEXT: addi sp, sp, -16
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; RV64I-LP64E-FPELIM-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-LP64E-FPELIM-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
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; RV64I-LP64E-FPELIM-NEXT: addi s0, sp, 16
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; RV64I-LP64E-FPELIM-NEXT: andi sp, sp, -16
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; RV64I-LP64E-FPELIM-NEXT: lw a0, 16(s0)
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; RV64I-LP64E-FPELIM-NEXT: addi sp, s0, -16
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; RV64I-LP64E-FPELIM-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-LP64E-FPELIM-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
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; RV64I-LP64E-FPELIM-NEXT: addi sp, sp, 16
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; RV64I-LP64E-FPELIM-NEXT: ret
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;
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; RV64I-LP64E-WITHFP-LABEL: callee_float_on_stack:
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; RV64I-LP64E-WITHFP: # %bb.0:
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; RV64I-LP64E-WITHFP-NEXT: addi sp, sp, -16
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; RV64I-LP64E-WITHFP-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-LP64E-WITHFP-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
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; RV64I-LP64E-WITHFP-NEXT: addi s0, sp, 16
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; RV64I-LP64E-WITHFP-NEXT: andi sp, sp, -16
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; RV64I-LP64E-WITHFP-NEXT: lw a0, 16(s0)
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; RV64I-LP64E-WITHFP-NEXT: addi sp, s0, -16
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; RV64I-LP64E-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-LP64E-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
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; RV64I-LP64E-WITHFP-NEXT: addi sp, sp, 16
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; RV64I-LP64E-WITHFP-NEXT: ret
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%1 = trunc i128 %d to i64
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%2 = bitcast float %e to i32
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%3 = sext i32 %2 to i64
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%4 = add i64 %1, %3
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ret i64 %3
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}
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define i64 @caller_float_on_stack() nounwind {
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; RV64I-LP64E-FPELIM-LABEL: caller_float_on_stack:
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; RV64I-LP64E-FPELIM: # %bb.0:
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; RV64I-LP64E-FPELIM-NEXT: addi sp, sp, -48
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; RV64I-LP64E-FPELIM-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
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; RV64I-LP64E-FPELIM-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
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; RV64I-LP64E-FPELIM-NEXT: addi s0, sp, 48
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; RV64I-LP64E-FPELIM-NEXT: andi sp, sp, -16
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; RV64I-LP64E-FPELIM-NEXT: lui a0, 264704
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; RV64I-LP64E-FPELIM-NEXT: sd a0, 16(sp)
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; RV64I-LP64E-FPELIM-NEXT: sd zero, 8(sp)
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; RV64I-LP64E-FPELIM-NEXT: li a1, 4
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; RV64I-LP64E-FPELIM-NEXT: li a0, 1
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; RV64I-LP64E-FPELIM-NEXT: li a2, 2
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; RV64I-LP64E-FPELIM-NEXT: li a4, 3
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; RV64I-LP64E-FPELIM-NEXT: sd a1, 0(sp)
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; RV64I-LP64E-FPELIM-NEXT: li a1, 0
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; RV64I-LP64E-FPELIM-NEXT: li a3, 0
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; RV64I-LP64E-FPELIM-NEXT: li a5, 0
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; RV64I-LP64E-FPELIM-NEXT: call callee_float_on_stack
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; RV64I-LP64E-FPELIM-NEXT: addi sp, s0, -48
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; RV64I-LP64E-FPELIM-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
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; RV64I-LP64E-FPELIM-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
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; RV64I-LP64E-FPELIM-NEXT: addi sp, sp, 48
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; RV64I-LP64E-FPELIM-NEXT: ret
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;
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; RV64I-LP64E-WITHFP-LABEL: caller_float_on_stack:
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; RV64I-LP64E-WITHFP: # %bb.0:
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; RV64I-LP64E-WITHFP-NEXT: addi sp, sp, -48
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; RV64I-LP64E-WITHFP-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
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; RV64I-LP64E-WITHFP-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
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; RV64I-LP64E-WITHFP-NEXT: addi s0, sp, 48
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; RV64I-LP64E-WITHFP-NEXT: andi sp, sp, -16
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; RV64I-LP64E-WITHFP-NEXT: lui a0, 264704
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; RV64I-LP64E-WITHFP-NEXT: sd a0, 16(sp)
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; RV64I-LP64E-WITHFP-NEXT: sd zero, 8(sp)
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; RV64I-LP64E-WITHFP-NEXT: li a1, 4
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; RV64I-LP64E-WITHFP-NEXT: li a0, 1
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; RV64I-LP64E-WITHFP-NEXT: li a2, 2
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; RV64I-LP64E-WITHFP-NEXT: li a4, 3
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; RV64I-LP64E-WITHFP-NEXT: sd a1, 0(sp)
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; RV64I-LP64E-WITHFP-NEXT: li a1, 0
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; RV64I-LP64E-WITHFP-NEXT: li a3, 0
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; RV64I-LP64E-WITHFP-NEXT: li a5, 0
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; RV64I-LP64E-WITHFP-NEXT: call callee_float_on_stack
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; RV64I-LP64E-WITHFP-NEXT: addi sp, s0, -48
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; RV64I-LP64E-WITHFP-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
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; RV64I-LP64E-WITHFP-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
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; RV64I-LP64E-WITHFP-NEXT: addi sp, sp, 48
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; RV64I-LP64E-WITHFP-NEXT: ret
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%1 = call i64 @callee_float_on_stack(i128 1, i128 2, i128 3, i128 4, float 5.0)
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ret i64 %1
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}
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define float @callee_tiny_scalar_ret() nounwind {
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; RV64I-LP64E-FPELIM-LABEL: callee_tiny_scalar_ret:
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; RV64I-LP64E-FPELIM: # %bb.0:
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; RV64I-LP64E-FPELIM-NEXT: lui a0, 260096
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; RV64I-LP64E-FPELIM-NEXT: ret
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;
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; RV64I-LP64E-WITHFP-LABEL: callee_tiny_scalar_ret:
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; RV64I-LP64E-WITHFP: # %bb.0:
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; RV64I-LP64E-WITHFP-NEXT: addi sp, sp, -16
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; RV64I-LP64E-WITHFP-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-LP64E-WITHFP-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
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; RV64I-LP64E-WITHFP-NEXT: addi s0, sp, 16
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; RV64I-LP64E-WITHFP-NEXT: lui a0, 260096
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; RV64I-LP64E-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-LP64E-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
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; RV64I-LP64E-WITHFP-NEXT: addi sp, sp, 16
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; RV64I-LP64E-WITHFP-NEXT: ret
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ret float 1.0
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}
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; The sign extension of the float return is necessary, as softened floats are
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; passed anyext.
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define i64 @caller_tiny_scalar_ret() nounwind {
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; RV64I-LP64E-FPELIM-LABEL: caller_tiny_scalar_ret:
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; RV64I-LP64E-FPELIM: # %bb.0:
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; RV64I-LP64E-FPELIM-NEXT: addi sp, sp, -8
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; RV64I-LP64E-FPELIM-NEXT: sd ra, 0(sp) # 8-byte Folded Spill
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; RV64I-LP64E-FPELIM-NEXT: call callee_tiny_scalar_ret
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; RV64I-LP64E-FPELIM-NEXT: sext.w a0, a0
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; RV64I-LP64E-FPELIM-NEXT: ld ra, 0(sp) # 8-byte Folded Reload
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; RV64I-LP64E-FPELIM-NEXT: addi sp, sp, 8
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; RV64I-LP64E-FPELIM-NEXT: ret
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;
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; RV64I-LP64E-WITHFP-LABEL: caller_tiny_scalar_ret:
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; RV64I-LP64E-WITHFP: # %bb.0:
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; RV64I-LP64E-WITHFP-NEXT: addi sp, sp, -16
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; RV64I-LP64E-WITHFP-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-LP64E-WITHFP-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
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; RV64I-LP64E-WITHFP-NEXT: addi s0, sp, 16
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; RV64I-LP64E-WITHFP-NEXT: call callee_tiny_scalar_ret
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; RV64I-LP64E-WITHFP-NEXT: sext.w a0, a0
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; RV64I-LP64E-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-LP64E-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
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; RV64I-LP64E-WITHFP-NEXT: addi sp, sp, 16
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; RV64I-LP64E-WITHFP-NEXT: ret
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%1 = call float @callee_tiny_scalar_ret()
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%2 = bitcast float %1 to i32
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%3 = sext i32 %2 to i64
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ret i64 %3
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}
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