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clang-p2996/llvm/test/CodeGen/RISCV/div-pow2.ll
Philip Reames 86eff6be68 [MachineCombiner] Use default latency model when no detailed model available 
This change adjusts the cost modeling used when the target does not have a schedule model with individual instruction latencies. After this change, we use the default latency information available from TargetSchedule. The default latency information essentially ends up treating most instructions as latency 1, with a few "expensive" ones getting a higher cost.

Previously, we unconditionally applied the first legal pattern - without any consideration of profitability. As a result, this change both prevents some patterns being applied, and changes which patterns are exercised. (i.e. previously the first pattern was applied, afterwards, maybe the second one is because the first wasn't profitable.)

The motivation here is two fold.

First, this brings the default behavior in line with the behavior when -mcpu or -mtune is specified. This improves test coverage, and generally makes it less likely we will have bad surprises when providing more information to the compiler.

Second, this enables some reassociation for ILP by default. Despite being unconditionally enabled, the prior code tended to "reassociate" repeatedly through an entire chain and simply moving the first operand to the end. The result was still a serial chain, just a different one. With this change, one of the intermediate transforms is unprofitable and we end up with a partially flattened tree.

Note that the resulting code diffs show significant room for improvement in the basic algorithm. I am intentionally excluding those from this patch.

For the test diffs, I don't seen any concerning regressions. I took a fairly close look at the RISCV ones, but only skimmed the x86 (particularly vector x86) changes.

Differential Revision: https://reviews.llvm.org/D141017
2023-01-20 09:28:20 -08:00

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefixes=RV32I
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefixes=RV64I
define i32 @sdiv32_pow2_2(i32 %a) {
; RV32I-LABEL: sdiv32_pow2_2:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: srli a1, a0, 31
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: srai a0, a0, 1
; RV32I-NEXT: ret
;
; RV64I-LABEL: sdiv32_pow2_2:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: srliw a1, a0, 31
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: sraiw a0, a0, 1
; RV64I-NEXT: ret
entry:
%div = sdiv i32 %a, 2
ret i32 %div
}
define i32 @sdiv32_pow2_negative_2(i32 %a) {
; RV32I-LABEL: sdiv32_pow2_negative_2:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: srli a1, a0, 31
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: srai a0, a0, 1
; RV32I-NEXT: neg a0, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: sdiv32_pow2_negative_2:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: srliw a1, a0, 31
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: sraiw a0, a0, 1
; RV64I-NEXT: neg a0, a0
; RV64I-NEXT: ret
entry:
%div = sdiv i32 %a, -2
ret i32 %div
}
define i32 @sdiv32_pow2_2048(i32 %a) {
; RV32I-LABEL: sdiv32_pow2_2048:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: srai a1, a0, 31
; RV32I-NEXT: srli a1, a1, 21
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: srai a0, a0, 11
; RV32I-NEXT: ret
;
; RV64I-LABEL: sdiv32_pow2_2048:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: sraiw a1, a0, 31
; RV64I-NEXT: srliw a1, a1, 21
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: sraiw a0, a0, 11
; RV64I-NEXT: ret
entry:
%div = sdiv i32 %a, 2048
ret i32 %div
}
define i32 @sdiv32_pow2_negative_2048(i32 %a) {
; RV32I-LABEL: sdiv32_pow2_negative_2048:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: srai a1, a0, 31
; RV32I-NEXT: srli a1, a1, 21
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: srai a0, a0, 11
; RV32I-NEXT: neg a0, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: sdiv32_pow2_negative_2048:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: sraiw a1, a0, 31
; RV64I-NEXT: srliw a1, a1, 21
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: sraiw a0, a0, 11
; RV64I-NEXT: neg a0, a0
; RV64I-NEXT: ret
entry:
%div = sdiv i32 %a, -2048
ret i32 %div
}
define i32 @sdiv32_pow2_4096(i32 %a) {
; RV32I-LABEL: sdiv32_pow2_4096:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: srai a1, a0, 31
; RV32I-NEXT: srli a1, a1, 20
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: srai a0, a0, 12
; RV32I-NEXT: ret
;
; RV64I-LABEL: sdiv32_pow2_4096:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: sraiw a1, a0, 31
; RV64I-NEXT: srliw a1, a1, 20
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: sraiw a0, a0, 12
; RV64I-NEXT: ret
entry:
%div = sdiv i32 %a, 4096
ret i32 %div
}
define i32 @sdiv32_pow2_negative_4096(i32 %a) {
; RV32I-LABEL: sdiv32_pow2_negative_4096:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: srai a1, a0, 31
; RV32I-NEXT: srli a1, a1, 20
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: srai a0, a0, 12
; RV32I-NEXT: neg a0, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: sdiv32_pow2_negative_4096:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: sraiw a1, a0, 31
; RV64I-NEXT: srliw a1, a1, 20
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: sraiw a0, a0, 12
; RV64I-NEXT: neg a0, a0
; RV64I-NEXT: ret
entry:
%div = sdiv i32 %a, -4096
ret i32 %div
}
define i32 @sdiv32_pow2_65536(i32 %a) {
; RV32I-LABEL: sdiv32_pow2_65536:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: srai a1, a0, 31
; RV32I-NEXT: srli a1, a1, 16
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: sdiv32_pow2_65536:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: sraiw a1, a0, 31
; RV64I-NEXT: srliw a1, a1, 16
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: sraiw a0, a0, 16
; RV64I-NEXT: ret
entry:
%div = sdiv i32 %a, 65536
ret i32 %div
}
define i32 @sdiv32_pow2_negative_65536(i32 %a) {
; RV32I-LABEL: sdiv32_pow2_negative_65536:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: srai a1, a0, 31
; RV32I-NEXT: srli a1, a1, 16
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: neg a0, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: sdiv32_pow2_negative_65536:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: sraiw a1, a0, 31
; RV64I-NEXT: srliw a1, a1, 16
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: sraiw a0, a0, 16
; RV64I-NEXT: neg a0, a0
; RV64I-NEXT: ret
entry:
%div = sdiv i32 %a, -65536
ret i32 %div
}
define i64 @sdiv64_pow2_2(i64 %a) {
; RV32I-LABEL: sdiv64_pow2_2:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: srli a2, a1, 31
; RV32I-NEXT: add a2, a0, a2
; RV32I-NEXT: srli a3, a2, 1
; RV32I-NEXT: sltu a0, a2, a0
; RV32I-NEXT: add a1, a1, a0
; RV32I-NEXT: slli a0, a1, 31
; RV32I-NEXT: or a0, a3, a0
; RV32I-NEXT: srai a1, a1, 1
; RV32I-NEXT: ret
;
; RV64I-LABEL: sdiv64_pow2_2:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: srli a1, a0, 63
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: srai a0, a0, 1
; RV64I-NEXT: ret
entry:
%div = sdiv i64 %a, 2
ret i64 %div
}
define i64 @sdiv64_pow2_negative_2(i64 %a) {
; RV32I-LABEL: sdiv64_pow2_negative_2:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: srli a2, a1, 31
; RV32I-NEXT: add a2, a0, a2
; RV32I-NEXT: srli a3, a2, 1
; RV32I-NEXT: sltu a0, a2, a0
; RV32I-NEXT: add a1, a1, a0
; RV32I-NEXT: slli a0, a1, 31
; RV32I-NEXT: or a3, a3, a0
; RV32I-NEXT: neg a0, a3
; RV32I-NEXT: snez a2, a3
; RV32I-NEXT: srai a1, a1, 1
; RV32I-NEXT: neg a1, a1
; RV32I-NEXT: sub a1, a1, a2
; RV32I-NEXT: ret
;
; RV64I-LABEL: sdiv64_pow2_negative_2:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: srli a1, a0, 63
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: srai a0, a0, 1
; RV64I-NEXT: neg a0, a0
; RV64I-NEXT: ret
entry:
%div = sdiv i64 %a, -2
ret i64 %div
}
define i64 @sdiv64_pow2_2048(i64 %a) {
; RV32I-LABEL: sdiv64_pow2_2048:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: srai a2, a1, 31
; RV32I-NEXT: srli a2, a2, 21
; RV32I-NEXT: add a2, a0, a2
; RV32I-NEXT: srli a3, a2, 11
; RV32I-NEXT: sltu a0, a2, a0
; RV32I-NEXT: add a1, a1, a0
; RV32I-NEXT: slli a0, a1, 21
; RV32I-NEXT: or a0, a3, a0
; RV32I-NEXT: srai a1, a1, 11
; RV32I-NEXT: ret
;
; RV64I-LABEL: sdiv64_pow2_2048:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: srai a1, a0, 63
; RV64I-NEXT: srli a1, a1, 53
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: srai a0, a0, 11
; RV64I-NEXT: ret
entry:
%div = sdiv i64 %a, 2048
ret i64 %div
}
define i64 @sdiv64_pow2_negative_2048(i64 %a) {
; RV32I-LABEL: sdiv64_pow2_negative_2048:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: srai a2, a1, 31
; RV32I-NEXT: srli a2, a2, 21
; RV32I-NEXT: add a2, a0, a2
; RV32I-NEXT: srli a3, a2, 11
; RV32I-NEXT: sltu a0, a2, a0
; RV32I-NEXT: add a1, a1, a0
; RV32I-NEXT: slli a0, a1, 21
; RV32I-NEXT: or a3, a3, a0
; RV32I-NEXT: neg a0, a3
; RV32I-NEXT: snez a2, a3
; RV32I-NEXT: srai a1, a1, 11
; RV32I-NEXT: neg a1, a1
; RV32I-NEXT: sub a1, a1, a2
; RV32I-NEXT: ret
;
; RV64I-LABEL: sdiv64_pow2_negative_2048:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: srai a1, a0, 63
; RV64I-NEXT: srli a1, a1, 53
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: srai a0, a0, 11
; RV64I-NEXT: neg a0, a0
; RV64I-NEXT: ret
entry:
%div = sdiv i64 %a, -2048
ret i64 %div
}
define i64 @sdiv64_pow2_4096(i64 %a) {
; RV32I-LABEL: sdiv64_pow2_4096:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: srai a2, a1, 31
; RV32I-NEXT: srli a2, a2, 20
; RV32I-NEXT: add a2, a0, a2
; RV32I-NEXT: srli a3, a2, 12
; RV32I-NEXT: sltu a0, a2, a0
; RV32I-NEXT: add a1, a1, a0
; RV32I-NEXT: slli a0, a1, 20
; RV32I-NEXT: or a0, a3, a0
; RV32I-NEXT: srai a1, a1, 12
; RV32I-NEXT: ret
;
; RV64I-LABEL: sdiv64_pow2_4096:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: srai a1, a0, 63
; RV64I-NEXT: srli a1, a1, 52
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: srai a0, a0, 12
; RV64I-NEXT: ret
entry:
%div = sdiv i64 %a, 4096
ret i64 %div
}
define i64 @sdiv64_pow2_negative_4096(i64 %a) {
; RV32I-LABEL: sdiv64_pow2_negative_4096:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: srai a2, a1, 31
; RV32I-NEXT: srli a2, a2, 20
; RV32I-NEXT: add a2, a0, a2
; RV32I-NEXT: srli a3, a2, 12
; RV32I-NEXT: sltu a0, a2, a0
; RV32I-NEXT: add a1, a1, a0
; RV32I-NEXT: slli a0, a1, 20
; RV32I-NEXT: or a3, a3, a0
; RV32I-NEXT: neg a0, a3
; RV32I-NEXT: snez a2, a3
; RV32I-NEXT: srai a1, a1, 12
; RV32I-NEXT: neg a1, a1
; RV32I-NEXT: sub a1, a1, a2
; RV32I-NEXT: ret
;
; RV64I-LABEL: sdiv64_pow2_negative_4096:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: srai a1, a0, 63
; RV64I-NEXT: srli a1, a1, 52
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: srai a0, a0, 12
; RV64I-NEXT: neg a0, a0
; RV64I-NEXT: ret
entry:
%div = sdiv i64 %a, -4096
ret i64 %div
}
define i64 @sdiv64_pow2_65536(i64 %a) {
; RV32I-LABEL: sdiv64_pow2_65536:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: srai a2, a1, 31
; RV32I-NEXT: srli a2, a2, 16
; RV32I-NEXT: add a2, a0, a2
; RV32I-NEXT: srli a3, a2, 16
; RV32I-NEXT: sltu a0, a2, a0
; RV32I-NEXT: add a1, a1, a0
; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: or a0, a3, a0
; RV32I-NEXT: srai a1, a1, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: sdiv64_pow2_65536:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: srai a1, a0, 63
; RV64I-NEXT: srli a1, a1, 48
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: srai a0, a0, 16
; RV64I-NEXT: ret
entry:
%div = sdiv i64 %a, 65536
ret i64 %div
}
define i64 @sdiv64_pow2_negative_65536(i64 %a) {
; RV32I-LABEL: sdiv64_pow2_negative_65536:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: srai a2, a1, 31
; RV32I-NEXT: srli a2, a2, 16
; RV32I-NEXT: add a2, a0, a2
; RV32I-NEXT: srli a3, a2, 16
; RV32I-NEXT: sltu a0, a2, a0
; RV32I-NEXT: add a1, a1, a0
; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: or a3, a3, a0
; RV32I-NEXT: neg a0, a3
; RV32I-NEXT: snez a2, a3
; RV32I-NEXT: srai a1, a1, 16
; RV32I-NEXT: neg a1, a1
; RV32I-NEXT: sub a1, a1, a2
; RV32I-NEXT: ret
;
; RV64I-LABEL: sdiv64_pow2_negative_65536:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: srai a1, a0, 63
; RV64I-NEXT: srli a1, a1, 48
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: srai a0, a0, 16
; RV64I-NEXT: neg a0, a0
; RV64I-NEXT: ret
entry:
%div = sdiv i64 %a, -65536
ret i64 %div
}
define i64 @sdiv64_pow2_8589934592(i64 %a) {
; RV32I-LABEL: sdiv64_pow2_8589934592:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: srli a2, a1, 31
; RV32I-NEXT: add a2, a1, a2
; RV32I-NEXT: srai a1, a1, 31
; RV32I-NEXT: add a1, a0, a1
; RV32I-NEXT: sltu a0, a1, a0
; RV32I-NEXT: add a1, a2, a0
; RV32I-NEXT: srai a0, a1, 1
; RV32I-NEXT: srai a1, a1, 31
; RV32I-NEXT: ret
;
; RV64I-LABEL: sdiv64_pow2_8589934592:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: srai a1, a0, 63
; RV64I-NEXT: srli a1, a1, 31
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: srai a0, a0, 33
; RV64I-NEXT: ret
entry:
%div = sdiv i64 %a, 8589934592 ; 2^33
ret i64 %div
}
define i64 @sdiv64_pow2_negative_8589934592(i64 %a) {
; RV32I-LABEL: sdiv64_pow2_negative_8589934592:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: srli a2, a1, 31
; RV32I-NEXT: add a2, a1, a2
; RV32I-NEXT: srai a1, a1, 31
; RV32I-NEXT: add a1, a0, a1
; RV32I-NEXT: sltu a0, a1, a0
; RV32I-NEXT: add a0, a2, a0
; RV32I-NEXT: srai a1, a0, 31
; RV32I-NEXT: srai a0, a0, 1
; RV32I-NEXT: snez a2, a0
; RV32I-NEXT: neg a1, a1
; RV32I-NEXT: sub a1, a1, a2
; RV32I-NEXT: neg a0, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: sdiv64_pow2_negative_8589934592:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: srai a1, a0, 63
; RV64I-NEXT: srli a1, a1, 31
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: srai a0, a0, 33
; RV64I-NEXT: neg a0, a0
; RV64I-NEXT: ret
entry:
%div = sdiv i64 %a, -8589934592 ; -2^33
ret i64 %div
}
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