d64d3c5a8f
SLLI and ADD are more compressible than SLLIW and ADDW. SLLI/ADD both have a 5-bit register encoding. SLLIW/ADDW have a 3-bit register encoding. They both require the dest to also be one of the sources. We aggressively form ADDW/SLLIW as it helps hasAllWBitUsers in RISCVISelDAGToDAG to not require recursion. So we need a pass to remove excessive -w suffixes. Differential Revision: https://reviews.llvm.org/D139948
126 lines
2.9 KiB
LLVM
126 lines
2.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s | FileCheck -check-prefix=RV32IF %s
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; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s | FileCheck -check-prefix=RV64IF %s
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define i32 @func_01() {
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; RV32IF-LABEL: func_01:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: frrm a0
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; RV32IF-NEXT: slli a0, a0, 2
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; RV32IF-NEXT: lui a1, 66
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; RV32IF-NEXT: addi a1, a1, 769
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; RV32IF-NEXT: srl a0, a1, a0
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; RV32IF-NEXT: andi a0, a0, 7
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: func_01:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: frrm a0
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; RV64IF-NEXT: slli a0, a0, 2
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; RV64IF-NEXT: lui a1, 66
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; RV64IF-NEXT: addiw a1, a1, 769
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; RV64IF-NEXT: srl a0, a1, a0
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; RV64IF-NEXT: andi a0, a0, 7
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; RV64IF-NEXT: ret
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%rm = call i32 @llvm.get.rounding()
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ret i32 %rm
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}
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define void @func_02(i32 %rm) {
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; RV32IF-LABEL: func_02:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: slli a0, a0, 2
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; RV32IF-NEXT: lui a1, 66
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; RV32IF-NEXT: addi a1, a1, 769
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; RV32IF-NEXT: srl a0, a1, a0
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; RV32IF-NEXT: andi a0, a0, 7
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; RV32IF-NEXT: fsrm a0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: func_02:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: slli a0, a0, 32
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; RV64IF-NEXT: srli a0, a0, 30
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; RV64IF-NEXT: lui a1, 66
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; RV64IF-NEXT: addiw a1, a1, 769
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; RV64IF-NEXT: srl a0, a1, a0
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; RV64IF-NEXT: andi a0, a0, 7
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; RV64IF-NEXT: fsrm a0
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; RV64IF-NEXT: ret
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call void @llvm.set.rounding(i32 %rm)
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ret void
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}
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define void @func_03() {
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; RV32IF-LABEL: func_03:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fsrmi 1
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: func_03:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fsrmi 1
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; RV64IF-NEXT: ret
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call void @llvm.set.rounding(i32 0)
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ret void
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}
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define void @func_04() {
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; RV32IF-LABEL: func_04:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fsrmi 0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: func_04:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fsrmi 0
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; RV64IF-NEXT: ret
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call void @llvm.set.rounding(i32 1)
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ret void
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}
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define void @func_05() {
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; RV32IF-LABEL: func_05:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fsrmi 3
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: func_05:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fsrmi 3
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; RV64IF-NEXT: ret
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call void @llvm.set.rounding(i32 2)
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ret void
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}
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define void @func_06() {
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; RV32IF-LABEL: func_06:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fsrmi 2
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: func_06:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fsrmi 2
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; RV64IF-NEXT: ret
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call void @llvm.set.rounding(i32 3)
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ret void
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}
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define void @func_07() {
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; RV32IF-LABEL: func_07:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fsrmi 4
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: func_07:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fsrmi 4
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; RV64IF-NEXT: ret
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call void @llvm.set.rounding(i32 4)
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ret void
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}
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declare void @llvm.set.rounding(i32)
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declare i32 @llvm.get.rounding()
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