c1c5da8f1f
fp-imm.ll and zfh-imm.ll test 0.0 and -0.0 while float/double/half-imm.ll tested other non-zero constants. It seems like they should all be tested together. There are slight coverage changes due to different command lines, but I'm not sure its meaningful. For example, we now don't test double 0.0 and -0.0 with only the F extension. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D156929
156 lines
5.0 KiB
LLVM
156 lines
5.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
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; RUN: -target-abi ilp32f < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
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; RUN: -target-abi lp64f < %s | FileCheck %s
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; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs \
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; RUN: -target-abi ilp32 < %s \
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; RUN: | FileCheck -check-prefix=RV32IZHINX %s
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; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \
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; RUN: -target-abi lp64 < %s \
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; RUN: | FileCheck -check-prefix=RV64IZHINX %s
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; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
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; RUN: -target-abi ilp32f < %s | FileCheck -check-prefixes=CHECKIZFHMIN %s
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; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
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; RUN: -target-abi lp64f < %s | FileCheck -check-prefixes=CHECKIZFHMIN %s
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; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs \
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; RUN: -target-abi ilp32 < %s \
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; RUN: | FileCheck -check-prefixes=CHECKIZHINXMIN %s
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; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs \
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; RUN: -target-abi lp64 < %s \
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; RUN: | FileCheck -check-prefixes=CHECKIZHINXMIN %s
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; TODO: constant pool shouldn't be necessary for RV32IZfh and RV64IZfh
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define half @half_imm() nounwind {
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; CHECK-LABEL: half_imm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, %hi(.LCPI0_0)
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; CHECK-NEXT: flh fa0, %lo(.LCPI0_0)(a0)
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; CHECK-NEXT: ret
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;
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; RV32IZHINX-LABEL: half_imm:
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; RV32IZHINX: # %bb.0:
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; RV32IZHINX-NEXT: lui a0, %hi(.LCPI0_0)
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; RV32IZHINX-NEXT: lh a0, %lo(.LCPI0_0)(a0)
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; RV32IZHINX-NEXT: ret
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;
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; RV64IZHINX-LABEL: half_imm:
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; RV64IZHINX: # %bb.0:
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; RV64IZHINX-NEXT: lui a0, %hi(.LCPI0_0)
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; RV64IZHINX-NEXT: lh a0, %lo(.LCPI0_0)(a0)
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; RV64IZHINX-NEXT: ret
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;
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; CHECKIZFHMIN-LABEL: half_imm:
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; CHECKIZFHMIN: # %bb.0:
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; CHECKIZFHMIN-NEXT: lui a0, %hi(.LCPI0_0)
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; CHECKIZFHMIN-NEXT: flh fa0, %lo(.LCPI0_0)(a0)
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; CHECKIZFHMIN-NEXT: ret
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;
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; CHECKIZHINXMIN-LABEL: half_imm:
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; CHECKIZHINXMIN: # %bb.0:
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; CHECKIZHINXMIN-NEXT: lui a0, %hi(.LCPI0_0)
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; CHECKIZHINXMIN-NEXT: lh a0, %lo(.LCPI0_0)(a0)
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; CHECKIZHINXMIN-NEXT: ret
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ret half 3.0
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}
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define half @half_imm_op(half %a) nounwind {
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; CHECK-LABEL: half_imm_op:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, %hi(.LCPI1_0)
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; CHECK-NEXT: flh fa5, %lo(.LCPI1_0)(a0)
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; CHECK-NEXT: fadd.h fa0, fa0, fa5
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; CHECK-NEXT: ret
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;
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; RV32IZHINX-LABEL: half_imm_op:
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; RV32IZHINX: # %bb.0:
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; RV32IZHINX-NEXT: lui a1, %hi(.LCPI1_0)
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; RV32IZHINX-NEXT: lh a1, %lo(.LCPI1_0)(a1)
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; RV32IZHINX-NEXT: fadd.h a0, a0, a1
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; RV32IZHINX-NEXT: ret
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;
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; RV64IZHINX-LABEL: half_imm_op:
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; RV64IZHINX: # %bb.0:
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; RV64IZHINX-NEXT: lui a1, %hi(.LCPI1_0)
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; RV64IZHINX-NEXT: lh a1, %lo(.LCPI1_0)(a1)
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; RV64IZHINX-NEXT: fadd.h a0, a0, a1
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; RV64IZHINX-NEXT: ret
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;
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; CHECKIZFHMIN-LABEL: half_imm_op:
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; CHECKIZFHMIN: # %bb.0:
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; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
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; CHECKIZFHMIN-NEXT: lui a0, 260096
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; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
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; CHECKIZFHMIN-NEXT: fadd.s fa5, fa5, fa4
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; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
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; CHECKIZFHMIN-NEXT: ret
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;
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; CHECKIZHINXMIN-LABEL: half_imm_op:
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; CHECKIZHINXMIN: # %bb.0:
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; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
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; CHECKIZHINXMIN-NEXT: lui a1, 260096
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; CHECKIZHINXMIN-NEXT: fadd.s a0, a0, a1
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; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
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; CHECKIZHINXMIN-NEXT: ret
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%1 = fadd half %a, 1.0
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ret half %1
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}
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define half @half_positive_zero(ptr %pf) nounwind {
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; CHECK-LABEL: half_positive_zero:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fmv.h.x fa0, zero
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; CHECK-NEXT: ret
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;
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; RV32IZHINX-LABEL: half_positive_zero:
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; RV32IZHINX: # %bb.0:
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; RV32IZHINX-NEXT: li a0, 0
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; RV32IZHINX-NEXT: ret
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;
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; RV64IZHINX-LABEL: half_positive_zero:
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; RV64IZHINX: # %bb.0:
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; RV64IZHINX-NEXT: li a0, 0
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; RV64IZHINX-NEXT: ret
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;
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; CHECKIZFHMIN-LABEL: half_positive_zero:
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; CHECKIZFHMIN: # %bb.0:
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; CHECKIZFHMIN-NEXT: fmv.h.x fa0, zero
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; CHECKIZFHMIN-NEXT: ret
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;
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; CHECKIZHINXMIN-LABEL: half_positive_zero:
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; CHECKIZHINXMIN: # %bb.0:
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; CHECKIZHINXMIN-NEXT: li a0, 0
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; CHECKIZHINXMIN-NEXT: ret
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ret half 0.0
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}
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define half @half_negative_zero(ptr %pf) nounwind {
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; CHECK-LABEL: half_negative_zero:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 1048568
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; CHECK-NEXT: fmv.h.x fa0, a0
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; CHECK-NEXT: ret
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;
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; RV32IZHINX-LABEL: half_negative_zero:
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; RV32IZHINX: # %bb.0:
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; RV32IZHINX-NEXT: lui a0, 1048568
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; RV32IZHINX-NEXT: ret
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;
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; RV64IZHINX-LABEL: half_negative_zero:
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; RV64IZHINX: # %bb.0:
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; RV64IZHINX-NEXT: lui a0, 1048568
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; RV64IZHINX-NEXT: ret
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;
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; CHECKIZFHMIN-LABEL: half_negative_zero:
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; CHECKIZFHMIN: # %bb.0:
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; CHECKIZFHMIN-NEXT: lui a0, 1048568
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; CHECKIZFHMIN-NEXT: fmv.h.x fa0, a0
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; CHECKIZFHMIN-NEXT: ret
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;
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; CHECKIZHINXMIN-LABEL: half_negative_zero:
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; CHECKIZHINXMIN: # %bb.0:
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; CHECKIZHINXMIN-NEXT: lui a0, 1048568
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; CHECKIZHINXMIN-NEXT: ret
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ret half -0.0
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}
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