b2c9eed0d7
On RISC-V, the `cycle` CSR holds a 64-bit count of the number of clock cycles executed by the core, from an arbitrary point in the past. This matches the intended semantics of `@llvm.readcyclecounter()`, which we currently leave to the default lowering (to the constant 0). With this patch, we will now correctly lower this intrinsic to the intended semantics, using the user-space instruction `rdcycle`. On 64-bit targets, we can directly lower to this instruction. On 32-bit targets, we need to do more, as `rdcycle` only returns the low 32-bits of the `cycle` CSR. In this case, we perform a custom lowering, based on the PowerPC lowering, using `rdcycleh` to obtain the high 32-bits of the `cycle` CSR. This custom lowering inserts a new basic block which detects overflow in the high 32-bits of the `cycle` CSR during reading (because multiple instructions are required to read). The emitted assembly matches the suggested assembly in the RISC-V specification. Differential Revision: https://reviews.llvm.org/D64125 llvm-svn: 365201
29 lines
914 B
LLVM
29 lines
914 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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; Verify that we lower @llvm.readcyclecounter() correctly.
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declare i64 @llvm.readcyclecounter()
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define i64 @test_builtin_readcyclecounter() nounwind {
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; RV32I-LABEL: test_builtin_readcyclecounter:
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; RV32I: # %bb.0:
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; RV32I-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
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; RV32I-NEXT: rdcycleh a1
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; RV32I-NEXT: rdcycle a0
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; RV32I-NEXT: rdcycleh a2
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; RV32I-NEXT: bne a1, a2, .LBB0_1
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; RV32I-NEXT: # %bb.2:
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: test_builtin_readcyclecounter:
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; RV64I: # %bb.0:
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; RV64I-NEXT: rdcycle a0
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; RV64I-NEXT: ret
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%1 = tail call i64 @llvm.readcyclecounter()
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ret i64 %1
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}
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