9396891271
We want to know the upper 33 bits of the And Input are zero. SExt only guarantees they are the same. We originally checked for SExt or ZExt when we were using isImpliedByDomCondition because a ZExt may have been changed to SExt before we visited the And. We are no longer using isImpliedByDomCondition so we can only look for zext with the nneg flag. While here, switch to PatternMatch to simplify the code. Fixes #78783
106 lines
5.5 KiB
LLVM
106 lines
5.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt %s -S -riscv-codegenprepare -mtriple=riscv64 | FileCheck %s
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; Make sure we convert the 4294967294 in for.body.preheader.new to -2 based on
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; the upper 33 bits being zero by the dominating condition %cmp3.
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define void @test2(ptr nocapture noundef %a, i32 noundef signext %n) {
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; CHECK-LABEL: @test2(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[N:%.*]], 0
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; CHECK-NEXT: br i1 [[CMP3]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_COND_CLEANUP:%.*]]
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; CHECK: for.body.preheader:
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; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext nneg i32 [[N]] to i64
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; CHECK-NEXT: [[XTRAITER:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 1
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; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i32 [[N]], 1
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; CHECK-NEXT: br i1 [[TMP0]], label [[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA:%.*]], label [[FOR_BODY_PREHEADER_NEW:%.*]]
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; CHECK: for.body.preheader.new:
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; CHECK-NEXT: [[UNROLL_ITER:%.*]] = and i64 [[WIDE_TRIP_COUNT]], -2
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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; CHECK: for.cond.cleanup.loopexit.unr-lcssa:
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; CHECK-NEXT: [[INDVARS_IV_UNR:%.*]] = phi i64 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[INDVARS_IV_NEXT_1:%.*]], [[FOR_BODY]] ]
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; CHECK-NEXT: [[LCMP_MOD_NOT:%.*]] = icmp eq i64 [[XTRAITER]], 0
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; CHECK-NEXT: br i1 [[LCMP_MOD_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY_EPIL:%.*]]
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; CHECK: for.body.epil:
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; CHECK-NEXT: [[ARRAYIDX_EPIL:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[INDVARS_IV_UNR]]
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; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX_EPIL]], align 4
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; CHECK-NEXT: [[ADD_EPIL:%.*]] = add nsw i32 [[TMP1]], 4
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; CHECK-NEXT: store i32 [[ADD_EPIL]], ptr [[ARRAYIDX_EPIL]], align 4
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; CHECK-NEXT: br label [[FOR_COND_CLEANUP]]
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; CHECK: for.cond.cleanup:
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; CHECK-NEXT: ret void
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; CHECK: for.body:
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; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[FOR_BODY_PREHEADER_NEW]] ], [ [[INDVARS_IV_NEXT_1]], [[FOR_BODY]] ]
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; CHECK-NEXT: [[NITER:%.*]] = phi i64 [ 0, [[FOR_BODY_PREHEADER_NEW]] ], [ [[NITER_NEXT_1:%.*]], [[FOR_BODY]] ]
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV]]
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; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 4
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; CHECK-NEXT: store i32 [[ADD]], ptr [[ARRAYIDX]], align 4
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; CHECK-NEXT: [[INDVARS_IV_NEXT:%.*]] = or i64 [[INDVARS_IV]], 1
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; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT]]
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; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX_1]], align 4
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; CHECK-NEXT: [[ADD_1:%.*]] = add nsw i32 [[TMP3]], 4
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; CHECK-NEXT: store i32 [[ADD_1]], ptr [[ARRAYIDX_1]], align 4
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; CHECK-NEXT: [[INDVARS_IV_NEXT_1]] = add nuw nsw i64 [[INDVARS_IV]], 2
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; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
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; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
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; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA]], label [[FOR_BODY]]
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;
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entry:
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%cmp3 = icmp sgt i32 %n, 0
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br i1 %cmp3, label %for.body.preheader, label %for.cond.cleanup
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for.body.preheader: ; preds = %entry
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%wide.trip.count = zext nneg i32 %n to i64
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%xtraiter = and i64 %wide.trip.count, 1
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%0 = icmp eq i32 %n, 1
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br i1 %0, label %for.cond.cleanup.loopexit.unr-lcssa, label %for.body.preheader.new
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for.body.preheader.new: ; preds = %for.body.preheader
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%unroll_iter = and i64 %wide.trip.count, 4294967294
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br label %for.body
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for.cond.cleanup.loopexit.unr-lcssa: ; preds = %for.body, %for.body.preheader
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%indvars.iv.unr = phi i64 [ 0, %for.body.preheader ], [ %indvars.iv.next.1, %for.body ]
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%lcmp.mod.not = icmp eq i64 %xtraiter, 0
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br i1 %lcmp.mod.not, label %for.cond.cleanup, label %for.body.epil
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for.body.epil: ; preds = %for.cond.cleanup.loopexit.unr-lcssa
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%arrayidx.epil = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.unr
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%1 = load i32, ptr %arrayidx.epil, align 4
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%add.epil = add nsw i32 %1, 4
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store i32 %add.epil, ptr %arrayidx.epil, align 4
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br label %for.cond.cleanup
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for.cond.cleanup: ; preds = %for.body.epil, %for.cond.cleanup.loopexit.unr-lcssa, %entry
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ret void
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for.body: ; preds = %for.body, %for.body.preheader.new
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%indvars.iv = phi i64 [ 0, %for.body.preheader.new ], [ %indvars.iv.next.1, %for.body ]
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%niter = phi i64 [ 0, %for.body.preheader.new ], [ %niter.next.1, %for.body ]
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%arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv
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%2 = load i32, ptr %arrayidx, align 4
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%add = add nsw i32 %2, 4
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store i32 %add, ptr %arrayidx, align 4
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%indvars.iv.next = or i64 %indvars.iv, 1
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%arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next
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%3 = load i32, ptr %arrayidx.1, align 4
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%add.1 = add nsw i32 %3, 4
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store i32 %add.1, ptr %arrayidx.1, align 4
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%indvars.iv.next.1 = add nuw nsw i64 %indvars.iv, 2
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%niter.next.1 = add i64 %niter, 2
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%niter.ncmp.1 = icmp eq i64 %niter.next.1, %unroll_iter
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br i1 %niter.ncmp.1, label %for.cond.cleanup.loopexit.unr-lcssa, label %for.body
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}
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; Make sure we do not change 4294967295 to -1 here.
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define i64 @bug(i32 %x) {
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; CHECK-LABEL: @bug(
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; CHECK-NEXT: [[A:%.*]] = sext i32 [[X:%.*]] to i64
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; CHECK-NEXT: [[B:%.*]] = and i64 [[A]], 4294967295
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; CHECK-NEXT: ret i64 [[B]]
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;
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%a = sext i32 %x to i64
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%b = and i64 %a, 4294967295
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ret i64 %b
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}
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