When we'd originally added unaligned-scalar-mem and unaligned-vector-mem, they were separated into two parts under the theory that some processor might implement one, but not the other. At the moment, we don't have evidence of such a processor. The C/C++ level interface, and the clang driver command lines have settled on a single unaligned flag which indicates both scalar and vector support unaligned. Given that, let's remove the test matrix complexity for a set of configurations which don't appear useful. Given these are internal feature names, I don't think we need to provide any forward compatibility. Anyone disagree? Note: The immediate trigger for this patch was finding another case where the unaligned-vector-mem wasn't being properly serialized to IR from clang which resulted in problems reproducing assembly from clang's -emit-llvm feature. Instead of fixing this, I decided getting rid of the complexity was the better approach.
45 lines
1.0 KiB
LLVM
45 lines
1.0 KiB
LLVM
; RUN: llc -mtriple=riscv64 -mcpu=sifive-u74 -verify-machineinstrs < %s | FileCheck %s
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; CHECK: .option push
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; CHECK-NEXT: .option arch, +v, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b
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define void @test1() "target-features"="+a,+d,+f,+m,+c,+v,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" {
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; CHECK-LABEL: test1
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; CHECK: .option pop
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entry:
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ret void
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}
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; CHECK: .option push
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; CHECK-NEXT: .option arch, +zihintntl
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define void @test2() "target-features"="+a,+d,+f,+m,+zihintntl,+zifencei" {
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; CHECK-LABEL: test2
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; CHECK: .option pop
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entry:
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ret void
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}
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; CHECK: .option push
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; CHECK-NEXT: .option arch, -a, -d, -f, -m
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define void @test3() "target-features"="-a,-d,-f,-m" {
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; CHECK-LABEL: test3
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; CHECK: .option pop
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entry:
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ret void
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}
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; CHECK-NOT: .option push
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define void @test4() {
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; CHECK-LABEL: test4
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; CHECK-NOT: .option pop
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entry:
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ret void
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}
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; CHECK-NOT: .option push
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define void @test5() "target-features"="+fast-unaligned-access" {
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; CHECK-LABEL: test5
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; CHECK-NOT: .option pop
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entry:
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ret void
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}
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