8624075105
The motivation of this change is simply to reduce test duplication. As can be seen in the (massive) test delta, we have many tests whose output differ only due to the use of addi on rv32 vs addiw on rv64 when the high bits are don't care. As an aside, we don't need to worry about the non-zero immediate restriction on the compressed variants because we're not directly forming the compressed variants. If we happen to get a zero immediate for the ADDI, then either a later optimization will strip the useless instruction or the encoder is responsible for not compressing the instruction.
195 lines
5.9 KiB
LLVM
195 lines
5.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s | FileCheck %s
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; This test has multiple opportunities for SimplifyDemandedBits after type
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; legalization. There are 2 opportunities on the chain feeding the LHS of the
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; shl. And one opportunity on the shift amount. We previously weren't managing
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; the DAGCombiner worklist correctly and failed to get the RHS.
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define i32 @foo(i32 %x, i32 %y, i32 %z) {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mul a0, a0, a0
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; CHECK-NEXT: addi a0, a0, 1
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; CHECK-NEXT: mul a0, a0, a0
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; CHECK-NEXT: add a0, a0, a2
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; CHECK-NEXT: addi a0, a0, 1
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; CHECK-NEXT: sllw a0, a0, a1
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; CHECK-NEXT: ret
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%b = mul i32 %x, %x
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%c = add i32 %b, 1
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%d = mul i32 %c, %c
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%e = add i32 %d, %z
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%f = add i32 %e, 1
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%g = shl i32 %f, %y
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ret i32 %g
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}
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; The sign bit of an nsw self multiply is 0. Make sure we can use this to
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; convert the AND constant to -8.
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define i64 @mul_self_nsw_sign(i64 %x) {
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; CHECK-LABEL: mul_self_nsw_sign:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mul a0, a0, a0
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; CHECK-NEXT: andi a0, a0, -8
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; CHECK-NEXT: ret
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%a = mul nsw i64 %x, %x
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%b = and i64 %a, 9223372036854775800
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ret i64 %b
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}
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; Make sure we sign extend the constant after type legalization to allow the
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; use of ori.
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define void @ori(ptr nocapture noundef %0) {
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; CHECK-LABEL: ori:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lw a1, 0(a0)
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; CHECK-NEXT: ori a1, a1, -2
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; CHECK-NEXT: sw a1, 0(a0)
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; CHECK-NEXT: ret
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%2 = load i32, ptr %0, align 4
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%3 = or i32 %2, -2
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store i32 %3, ptr %0, align 4
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ret void
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}
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; Make sure we sign extend the constant after type legalization to allow the
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; use of xori.
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define void @xori(ptr nocapture noundef %0) {
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; CHECK-LABEL: xori:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lw a1, 0(a0)
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; CHECK-NEXT: xori a1, a1, -5
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; CHECK-NEXT: sw a1, 0(a0)
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; CHECK-NEXT: ret
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%2 = load i32, ptr %0, align 4
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%3 = xor i32 %2, -5
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store i32 %3, ptr %0, align 4
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ret void
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}
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; Make sure we sign extend the constant after type legalization to allow the
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; shorter constant materialization.
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define void @or_signbit(ptr nocapture noundef %0) {
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; CHECK-LABEL: or_signbit:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lw a1, 0(a0)
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; CHECK-NEXT: lui a2, 524288
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; CHECK-NEXT: or a1, a1, a2
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; CHECK-NEXT: sw a1, 0(a0)
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; CHECK-NEXT: ret
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%2 = load i32, ptr %0, align 4
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%3 = or i32 %2, -2147483648
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store i32 %3, ptr %0, align 4
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ret void
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}
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; Make sure we sign extend the constant after type legalization to allow the
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; shorter constant materialization.
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define void @xor_signbit(ptr nocapture noundef %0) {
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; CHECK-LABEL: xor_signbit:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lw a1, 0(a0)
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; CHECK-NEXT: lui a2, 524288
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; CHECK-NEXT: xor a1, a1, a2
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; CHECK-NEXT: sw a1, 0(a0)
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; CHECK-NEXT: ret
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%2 = load i32, ptr %0, align 4
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%3 = xor i32 %2, -2147483648
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store i32 %3, ptr %0, align 4
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ret void
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}
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; Type legalization inserts a sext_inreg after the sub. This causes the
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; constant for the AND to be turned into 0xfffffff8. Then SimplifyDemandedBits
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; removes the sext_inreg from the path to the store. This prevents
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; TargetShrinkDemandedConstant from being able to restore the lost upper bits
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; from the and mask to allow andi. ISel is able to recover the lost sext_inreg
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; using hasAllWUsers. We also use hasAllWUsers to recover the ANDI.
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define signext i32 @andi_sub_cse(i32 signext %0, i32 signext %1, ptr %2) {
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; CHECK-LABEL: andi_sub_cse:
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; CHECK: # %bb.0:
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; CHECK-NEXT: andi a0, a0, -8
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; CHECK-NEXT: subw a0, a0, a1
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; CHECK-NEXT: sw a0, 0(a2)
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; CHECK-NEXT: ret
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%4 = and i32 %0, -8
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%5 = sub i32 %4, %1
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store i32 %5, ptr %2, align 4
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ret i32 %5
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}
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define signext i32 @addi_sub_cse(i32 signext %0, i32 signext %1, ptr %2) {
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; CHECK-LABEL: addi_sub_cse:
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; CHECK: # %bb.0:
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; CHECK-NEXT: subw a0, a0, a1
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; CHECK-NEXT: addiw a0, a0, -8
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; CHECK-NEXT: sw a0, 0(a2)
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; CHECK-NEXT: ret
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%4 = add i32 %0, -8
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%5 = sub i32 %4, %1
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store i32 %5, ptr %2, align 4
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ret i32 %5
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}
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define signext i32 @xori_sub_cse(i32 signext %0, i32 signext %1, ptr %2) {
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; CHECK-LABEL: xori_sub_cse:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xori a0, a0, -8
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; CHECK-NEXT: subw a0, a0, a1
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; CHECK-NEXT: sw a0, 0(a2)
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; CHECK-NEXT: ret
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%4 = xor i32 %0, -8
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%5 = sub i32 %4, %1
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store i32 %5, ptr %2, align 4
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ret i32 %5
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}
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define signext i32 @ori_sub_cse(i32 signext %0, i32 signext %1, ptr %2) {
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; CHECK-LABEL: ori_sub_cse:
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; CHECK: # %bb.0:
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; CHECK-NEXT: ori a0, a0, -8
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; CHECK-NEXT: subw a0, a0, a1
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; CHECK-NEXT: sw a0, 0(a2)
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; CHECK-NEXT: ret
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%4 = or i32 %0, -8
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%5 = sub i32 %4, %1
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store i32 %5, ptr %2, align 4
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ret i32 %5
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}
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; SimplifyDemandedBits breaks the ANDI by turning -8 into 0xfffffff8. This
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; gets CSEd with the AND needed for type legalizing the lshr. This increases
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; the use count of the AND with 0xfffffff8 making TargetShrinkDemandedConstant
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; unable to restore it to 0xffffffff for the lshr and -8 for the AND to use
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; ANDI.
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; Instead we rely on ISel to form srliw even though the AND has multiple uses
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; and the mask has missing 1s where bits will be shifted out. This reduces the
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; use count of the AND and we can use hasAllWUsers to form ANDI.
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define signext i32 @andi_srliw(i32 signext %0, ptr %1, i32 signext %2) {
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; CHECK-LABEL: andi_srliw:
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; CHECK: # %bb.0:
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; CHECK-NEXT: andi a3, a0, -8
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; CHECK-NEXT: srliw a4, a0, 3
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; CHECK-NEXT: addw a0, a3, a2
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; CHECK-NEXT: sw a4, 0(a1)
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; CHECK-NEXT: ret
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%4 = and i32 %0, -8
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%5 = lshr i32 %0, 3
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store i32 %5, ptr %1, align 4
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%6 = add i32 %4, %2
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ret i32 %6
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}
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define i32 @and_or(i32 signext %x) {
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; CHECK-LABEL: and_or:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: ori a0, a0, 255
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; CHECK-NEXT: slli a0, a0, 48
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; CHECK-NEXT: srli a0, a0, 48
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; CHECK-NEXT: ret
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entry:
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%and = and i32 %x, 65280
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%or = or i32 %and, 255
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ret i32 %or
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}
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