29e8bfc13c
This commit handles vector arguments/return for function definition/call, the new class RVVArgDispatcher is added for doing all vector register assignment including mask types, data types as well as tuple types. It precomputes the register number for each argument as per https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc#standard-vector-calling-convention-variant and it's passed to calling convention function to handle all vector arguments. Depends on: #78550
252 lines
9.3 KiB
LLVM
252 lines
9.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+m,+v < %s | FileCheck %s --check-prefixes=CHECK,RV32
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; RUN: llc -mtriple=riscv64 -mattr=+m,+v < %s | FileCheck %s --check-prefixes=CHECK,RV64
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; Check that we correctly scale the split part indirect offsets by VSCALE.
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define <vscale x 32 x i32> @callee_scalable_vector_split_indirect(<vscale x 32 x i32> %x, <vscale x 32 x i32> %y) {
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; CHECK-LABEL: callee_scalable_vector_split_indirect:
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; CHECK: # %bb.0:
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; CHECK-NEXT: csrr a1, vlenb
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; CHECK-NEXT: slli a1, a1, 3
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; CHECK-NEXT: add a1, a0, a1
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; CHECK-NEXT: vl8re32.v v24, (a0)
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; CHECK-NEXT: vl8re32.v v0, (a1)
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; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
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; CHECK-NEXT: vadd.vv v8, v8, v24
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; CHECK-NEXT: vadd.vv v16, v16, v0
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; CHECK-NEXT: ret
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%a = add <vscale x 32 x i32> %x, %y
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ret <vscale x 32 x i32> %a
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}
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; Call the function above. Check that we set the arguments correctly.
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define <vscale x 32 x i32> @caller_scalable_vector_split_indirect(<vscale x 32 x i32> %x) {
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; RV32-LABEL: caller_scalable_vector_split_indirect:
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; RV32: # %bb.0:
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; RV32-NEXT: addi sp, sp, -144
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; RV32-NEXT: .cfi_def_cfa_offset 144
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; RV32-NEXT: sw ra, 140(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s0, 136(sp) # 4-byte Folded Spill
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; RV32-NEXT: .cfi_offset ra, -4
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; RV32-NEXT: .cfi_offset s0, -8
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; RV32-NEXT: addi s0, sp, 144
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; RV32-NEXT: .cfi_def_cfa s0, 0
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; RV32-NEXT: csrr a0, vlenb
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; RV32-NEXT: slli a0, a0, 4
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; RV32-NEXT: sub sp, sp, a0
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; RV32-NEXT: andi sp, sp, -128
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; RV32-NEXT: addi a0, sp, 128
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; RV32-NEXT: vs8r.v v8, (a0)
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; RV32-NEXT: csrr a1, vlenb
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; RV32-NEXT: slli a1, a1, 3
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; RV32-NEXT: add a0, a0, a1
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; RV32-NEXT: vs8r.v v16, (a0)
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; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, ma
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; RV32-NEXT: vmv.v.i v8, 0
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; RV32-NEXT: addi a0, sp, 128
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; RV32-NEXT: vmv.v.i v16, 0
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; RV32-NEXT: call callee_scalable_vector_split_indirect
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; RV32-NEXT: addi sp, s0, -144
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; RV32-NEXT: lw ra, 140(sp) # 4-byte Folded Reload
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; RV32-NEXT: lw s0, 136(sp) # 4-byte Folded Reload
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; RV32-NEXT: addi sp, sp, 144
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; RV32-NEXT: ret
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;
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; RV64-LABEL: caller_scalable_vector_split_indirect:
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; RV64: # %bb.0:
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; RV64-NEXT: addi sp, sp, -144
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; RV64-NEXT: .cfi_def_cfa_offset 144
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; RV64-NEXT: sd ra, 136(sp) # 8-byte Folded Spill
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; RV64-NEXT: sd s0, 128(sp) # 8-byte Folded Spill
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; RV64-NEXT: .cfi_offset ra, -8
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; RV64-NEXT: .cfi_offset s0, -16
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; RV64-NEXT: addi s0, sp, 144
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; RV64-NEXT: .cfi_def_cfa s0, 0
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; RV64-NEXT: csrr a0, vlenb
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; RV64-NEXT: slli a0, a0, 4
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; RV64-NEXT: sub sp, sp, a0
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; RV64-NEXT: andi sp, sp, -128
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; RV64-NEXT: addi a0, sp, 128
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; RV64-NEXT: vs8r.v v8, (a0)
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; RV64-NEXT: csrr a1, vlenb
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; RV64-NEXT: slli a1, a1, 3
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; RV64-NEXT: add a0, a0, a1
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; RV64-NEXT: vs8r.v v16, (a0)
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; RV64-NEXT: vsetvli a0, zero, e32, m8, ta, ma
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; RV64-NEXT: vmv.v.i v8, 0
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; RV64-NEXT: addi a0, sp, 128
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; RV64-NEXT: vmv.v.i v16, 0
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; RV64-NEXT: call callee_scalable_vector_split_indirect
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; RV64-NEXT: addi sp, s0, -144
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; RV64-NEXT: ld ra, 136(sp) # 8-byte Folded Reload
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; RV64-NEXT: ld s0, 128(sp) # 8-byte Folded Reload
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; RV64-NEXT: addi sp, sp, 144
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; RV64-NEXT: ret
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%c = alloca i64
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%a = call <vscale x 32 x i32> @callee_scalable_vector_split_indirect(<vscale x 32 x i32> zeroinitializer, <vscale x 32 x i32> %x)
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ret <vscale x 32 x i32> %a
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}
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define {<vscale x 4 x i32>, <vscale x 4 x i32>} @caller_tuple_return() {
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; RV32-LABEL: caller_tuple_return:
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; RV32: # %bb.0:
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32-NEXT: .cfi_offset ra, -4
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; RV32-NEXT: call callee_tuple_return
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; RV32-NEXT: vmv2r.v v12, v8
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; RV32-NEXT: vmv2r.v v8, v10
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; RV32-NEXT: vmv2r.v v10, v12
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; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: ret
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;
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; RV64-LABEL: caller_tuple_return:
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; RV64: # %bb.0:
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; RV64-NEXT: addi sp, sp, -16
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; RV64-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64-NEXT: .cfi_offset ra, -8
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; RV64-NEXT: call callee_tuple_return
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; RV64-NEXT: vmv2r.v v12, v8
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; RV64-NEXT: vmv2r.v v8, v10
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; RV64-NEXT: vmv2r.v v10, v12
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; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64-NEXT: addi sp, sp, 16
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; RV64-NEXT: ret
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%a = call {<vscale x 4 x i32>, <vscale x 4 x i32>} @callee_tuple_return()
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%b = extractvalue {<vscale x 4 x i32>, <vscale x 4 x i32>} %a, 0
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%c = extractvalue {<vscale x 4 x i32>, <vscale x 4 x i32>} %a, 1
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%d = insertvalue {<vscale x 4 x i32>, <vscale x 4 x i32>} poison, <vscale x 4 x i32> %c, 0
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%e = insertvalue {<vscale x 4 x i32>, <vscale x 4 x i32>} %d, <vscale x 4 x i32> %b, 1
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ret {<vscale x 4 x i32>, <vscale x 4 x i32>} %e
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}
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declare {<vscale x 4 x i32>, <vscale x 4 x i32>} @callee_tuple_return()
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define void @caller_tuple_argument({<vscale x 4 x i32>, <vscale x 4 x i32>} %x) {
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; RV32-LABEL: caller_tuple_argument:
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; RV32: # %bb.0:
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32-NEXT: .cfi_offset ra, -4
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; RV32-NEXT: vmv2r.v v12, v8
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; RV32-NEXT: vmv2r.v v8, v10
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; RV32-NEXT: vmv2r.v v10, v12
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; RV32-NEXT: call callee_tuple_argument
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; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: ret
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;
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; RV64-LABEL: caller_tuple_argument:
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; RV64: # %bb.0:
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; RV64-NEXT: addi sp, sp, -16
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; RV64-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64-NEXT: .cfi_offset ra, -8
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; RV64-NEXT: vmv2r.v v12, v8
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; RV64-NEXT: vmv2r.v v8, v10
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; RV64-NEXT: vmv2r.v v10, v12
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; RV64-NEXT: call callee_tuple_argument
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; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64-NEXT: addi sp, sp, 16
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; RV64-NEXT: ret
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%a = extractvalue {<vscale x 4 x i32>, <vscale x 4 x i32>} %x, 0
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%b = extractvalue {<vscale x 4 x i32>, <vscale x 4 x i32>} %x, 1
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%c = insertvalue {<vscale x 4 x i32>, <vscale x 4 x i32>} poison, <vscale x 4 x i32> %b, 0
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%d = insertvalue {<vscale x 4 x i32>, <vscale x 4 x i32>} %c, <vscale x 4 x i32> %a, 1
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call void @callee_tuple_argument({<vscale x 4 x i32>, <vscale x 4 x i32>} %d)
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ret void
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}
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declare void @callee_tuple_argument({<vscale x 4 x i32>, <vscale x 4 x i32>})
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; %0 -> v8
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; %1 -> v9
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define <vscale x 1 x i64> @case1(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1) {
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; CHECK-LABEL: case1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
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; CHECK-NEXT: vadd.vv v8, v8, v9
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; CHECK-NEXT: ret
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%a = add <vscale x 1 x i64> %0, %1
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ret <vscale x 1 x i64> %a
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}
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; %0 -> v8
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; %1 -> v10-v11
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; %2 -> v9
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define <vscale x 1 x i64> @case2_1(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2) {
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; CHECK-LABEL: case2_1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
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; CHECK-NEXT: vadd.vv v8, v8, v9
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; CHECK-NEXT: ret
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%a = add <vscale x 1 x i64> %0, %2
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ret <vscale x 1 x i64> %a
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}
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define <vscale x 2 x i64> @case2_2(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2) {
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; CHECK-LABEL: case2_2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
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; CHECK-NEXT: vadd.vv v8, v10, v10
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; CHECK-NEXT: ret
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%a = add <vscale x 2 x i64> %1, %1
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ret <vscale x 2 x i64> %a
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}
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; %0 -> v8
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; %1 -> {v10-v11, v12-v13}
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; %2 -> v9
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define <vscale x 1 x i64> @case3_1(<vscale x 1 x i64> %0, {<vscale x 2 x i64>, <vscale x 2 x i64>} %1, <vscale x 1 x i64> %2) {
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; CHECK-LABEL: case3_1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
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; CHECK-NEXT: vadd.vv v8, v8, v9
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; CHECK-NEXT: ret
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%add = add <vscale x 1 x i64> %0, %2
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ret <vscale x 1 x i64> %add
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}
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define <vscale x 2 x i64> @case3_2(<vscale x 1 x i64> %0, {<vscale x 2 x i64>, <vscale x 2 x i64>} %1, <vscale x 1 x i64> %2) {
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; CHECK-LABEL: case3_2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
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; CHECK-NEXT: vadd.vv v8, v10, v12
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; CHECK-NEXT: ret
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%a = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, 0
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%b = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, 1
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%add = add <vscale x 2 x i64> %a, %b
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ret <vscale x 2 x i64> %add
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}
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; %0 -> v8
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; %1 -> {by-ref, by-ref}
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; %2 -> v9
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define <vscale x 8 x i64> @case4_1(<vscale x 1 x i64> %0, {<vscale x 8 x i64>, <vscale x 8 x i64>} %1, <vscale x 1 x i64> %2) {
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; CHECK-LABEL: case4_1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: csrr a1, vlenb
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; CHECK-NEXT: slli a1, a1, 3
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; CHECK-NEXT: add a1, a0, a1
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; CHECK-NEXT: vl8re64.v v8, (a1)
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; CHECK-NEXT: vl8re64.v v16, (a0)
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; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
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; CHECK-NEXT: vadd.vv v8, v16, v8
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; CHECK-NEXT: ret
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%a = extractvalue { <vscale x 8 x i64>, <vscale x 8 x i64> } %1, 0
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%b = extractvalue { <vscale x 8 x i64>, <vscale x 8 x i64> } %1, 1
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%add = add <vscale x 8 x i64> %a, %b
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ret <vscale x 8 x i64> %add
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}
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define <vscale x 1 x i64> @case4_2(<vscale x 1 x i64> %0, {<vscale x 8 x i64>, <vscale x 8 x i64>} %1, <vscale x 1 x i64> %2) {
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; CHECK-LABEL: case4_2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
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; CHECK-NEXT: vadd.vv v8, v8, v9
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; CHECK-NEXT: ret
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%add = add <vscale x 1 x i64> %0, %2
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ret <vscale x 1 x i64> %add
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}
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