0fee2115bb
Some fixed vector tests in test/CodeGen/RISCV/rvv have multiple run lines that check various configurations of -riscv-v-fixed-length-vector-lmul-max. From what I understand this flag was introduced in the early days of fixed length vector support, but now that fixed vector codegen has matured I'm not sure if it's as relevant today. This patch proposes to remove the various lmul-max run lines from the tests to make them more readable, and any changes to fixed vector codegen easier to review. We have removed them before for the same reason, so this would take care of the remaining test cases: https://reviews.llvm.org/D157973#4593268 (I don't have any strong motivation to remove the actual flag itself, my own personal motivation is just to clean up the tests)
244 lines
6.8 KiB
LLVM
244 lines
6.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
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; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
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declare <2 x i8> @llvm.experimental.stepvector.v2i8()
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define <2 x i8> @stepvector_v2i8() {
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; CHECK-LABEL: stepvector_v2i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <2 x i8> @llvm.experimental.stepvector.v2i8()
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ret <2 x i8> %v
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}
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declare <3 x i8> @llvm.experimental.stepvector.v3i8()
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define <3 x i8> @stepvector_v3i8() {
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; CHECK-LABEL: stepvector_v3i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <3 x i8> @llvm.experimental.stepvector.v3i8()
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ret <3 x i8> %v
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}
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declare <4 x i8> @llvm.experimental.stepvector.v4i8()
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define <4 x i8> @stepvector_v4i8() {
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; CHECK-LABEL: stepvector_v4i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <4 x i8> @llvm.experimental.stepvector.v4i8()
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ret <4 x i8> %v
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}
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declare <8 x i8> @llvm.experimental.stepvector.v8i8()
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define <8 x i8> @stepvector_v8i8() {
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; CHECK-LABEL: stepvector_v8i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <8 x i8> @llvm.experimental.stepvector.v8i8()
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ret <8 x i8> %v
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}
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declare <16 x i8> @llvm.experimental.stepvector.v16i8()
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define <16 x i8> @stepvector_v16i8() {
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; CHECK-LABEL: stepvector_v16i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <16 x i8> @llvm.experimental.stepvector.v16i8()
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ret <16 x i8> %v
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}
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declare <2 x i16> @llvm.experimental.stepvector.v2i16()
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define <2 x i16> @stepvector_v2i16() {
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; CHECK-LABEL: stepvector_v2i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <2 x i16> @llvm.experimental.stepvector.v2i16()
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ret <2 x i16> %v
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}
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declare <4 x i16> @llvm.experimental.stepvector.v4i16()
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define <4 x i16> @stepvector_v4i16() {
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; CHECK-LABEL: stepvector_v4i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <4 x i16> @llvm.experimental.stepvector.v4i16()
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ret <4 x i16> %v
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}
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declare <8 x i16> @llvm.experimental.stepvector.v8i16()
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define <8 x i16> @stepvector_v8i16() {
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; CHECK-LABEL: stepvector_v8i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <8 x i16> @llvm.experimental.stepvector.v8i16()
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ret <8 x i16> %v
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}
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declare <16 x i16> @llvm.experimental.stepvector.v16i16()
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define <16 x i16> @stepvector_v16i16() {
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; CHECK-LABEL: stepvector_v16i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <16 x i16> @llvm.experimental.stepvector.v16i16()
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ret <16 x i16> %v
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}
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declare <2 x i32> @llvm.experimental.stepvector.v2i32()
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define <2 x i32> @stepvector_v2i32() {
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; CHECK-LABEL: stepvector_v2i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <2 x i32> @llvm.experimental.stepvector.v2i32()
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ret <2 x i32> %v
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}
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declare <4 x i32> @llvm.experimental.stepvector.v4i32()
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define <4 x i32> @stepvector_v4i32() {
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; CHECK-LABEL: stepvector_v4i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <4 x i32> @llvm.experimental.stepvector.v4i32()
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ret <4 x i32> %v
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}
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declare <8 x i32> @llvm.experimental.stepvector.v8i32()
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define <8 x i32> @stepvector_v8i32() {
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; CHECK-LABEL: stepvector_v8i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <8 x i32> @llvm.experimental.stepvector.v8i32()
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ret <8 x i32> %v
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}
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declare <16 x i32> @llvm.experimental.stepvector.v16i32()
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define <16 x i32> @stepvector_v16i32() {
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; CHECK-LABEL: stepvector_v16i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <16 x i32> @llvm.experimental.stepvector.v16i32()
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ret <16 x i32> %v
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}
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declare <2 x i64> @llvm.experimental.stepvector.v2i64()
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define <2 x i64> @stepvector_v2i64() {
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; RV32-LABEL: stepvector_v2i64:
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; RV32: # %bb.0:
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; RV32-NEXT: lui a0, 16
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; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; RV32-NEXT: vmv.s.x v9, a0
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; RV32-NEXT: vsext.vf4 v8, v9
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; RV32-NEXT: ret
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;
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; RV64-LABEL: stepvector_v2i64:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
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; RV64-NEXT: vid.v v8
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; RV64-NEXT: ret
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%v = call <2 x i64> @llvm.experimental.stepvector.v2i64()
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ret <2 x i64> %v
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}
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declare <4 x i64> @llvm.experimental.stepvector.v4i64()
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define <4 x i64> @stepvector_v4i64() {
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; RV32-LABEL: stepvector_v4i64:
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; RV32: # %bb.0:
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; RV32-NEXT: lui a0, %hi(.LCPI14_0)
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; RV32-NEXT: addi a0, a0, %lo(.LCPI14_0)
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; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
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; RV32-NEXT: vle8.v v10, (a0)
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; RV32-NEXT: vsext.vf4 v8, v10
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; RV32-NEXT: ret
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;
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; RV64-LABEL: stepvector_v4i64:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; RV64-NEXT: vid.v v8
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; RV64-NEXT: ret
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%v = call <4 x i64> @llvm.experimental.stepvector.v4i64()
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ret <4 x i64> %v
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}
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declare <8 x i64> @llvm.experimental.stepvector.v8i64()
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define <8 x i64> @stepvector_v8i64() {
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; RV32-LABEL: stepvector_v8i64:
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; RV32: # %bb.0:
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; RV32-NEXT: lui a0, %hi(.LCPI15_0)
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; RV32-NEXT: addi a0, a0, %lo(.LCPI15_0)
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; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
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; RV32-NEXT: vle8.v v12, (a0)
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; RV32-NEXT: vsext.vf4 v8, v12
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; RV32-NEXT: ret
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;
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; RV64-LABEL: stepvector_v8i64:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
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; RV64-NEXT: vid.v v8
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; RV64-NEXT: ret
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%v = call <8 x i64> @llvm.experimental.stepvector.v8i64()
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ret <8 x i64> %v
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}
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declare <16 x i64> @llvm.experimental.stepvector.v16i64()
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define <16 x i64> @stepvector_v16i64() {
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; RV32-LABEL: stepvector_v16i64:
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; RV32: # %bb.0:
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; RV32-NEXT: lui a0, %hi(.LCPI16_0)
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; RV32-NEXT: addi a0, a0, %lo(.LCPI16_0)
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; RV32-NEXT: li a1, 32
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; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
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; RV32-NEXT: vle8.v v16, (a0)
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; RV32-NEXT: vsext.vf4 v8, v16
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; RV32-NEXT: ret
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;
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; RV64-LABEL: stepvector_v16i64:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
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; RV64-NEXT: vid.v v8
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; RV64-NEXT: ret
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%v = call <16 x i64> @llvm.experimental.stepvector.v16i64()
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ret <16 x i64> %v
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}
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