afc7cc7b12
All of these test cases had iXLen in their name which got replaced by sed. This prevented FileCheck from finding the function. The other test cases in these files do not have that issue.
229 lines
8.0 KiB
LLVM
229 lines
8.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+f,+d \
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; RUN: -target-abi=ilp32d -verify-machineinstrs | FileCheck %s --check-prefix=RV32
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; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv64 -mattr=+v,+f,+d \
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; RUN: -target-abi=lp64d -verify-machineinstrs | FileCheck %s --check-prefix=RV64-i32
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; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+f,+d \
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; RUN: -target-abi=lp64d -verify-machineinstrs | FileCheck %s --check-prefix=RV64-i64
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define <vscale x 1 x iXLen> @lrint_nxv1f32(<vscale x 1 x float> %x) {
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; RV32-LABEL: lrint_nxv1f32:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
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; RV32-NEXT: vfcvt.x.f.v v8, v8
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; RV32-NEXT: ret
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;
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; RV64-i32-LABEL: lrint_nxv1f32:
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; RV64-i32: # %bb.0:
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; RV64-i32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
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; RV64-i32-NEXT: vfcvt.x.f.v v8, v8
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; RV64-i32-NEXT: ret
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;
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; RV64-i64-LABEL: lrint_nxv1f32:
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; RV64-i64: # %bb.0:
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; RV64-i64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
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; RV64-i64-NEXT: vfwcvt.x.f.v v9, v8
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; RV64-i64-NEXT: vmv1r.v v8, v9
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; RV64-i64-NEXT: ret
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%a = call <vscale x 1 x iXLen> @llvm.lrint.nxv1iXLen.nxv1f32(<vscale x 1 x float> %x)
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ret <vscale x 1 x iXLen> %a
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}
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declare <vscale x 1 x iXLen> @llvm.lrint.nxv1iXLen.nxv1f32(<vscale x 1 x float>)
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define <vscale x 2 x iXLen> @lrint_nxv2f32(<vscale x 2 x float> %x) {
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; RV32-LABEL: lrint_nxv2f32:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, ma
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; RV32-NEXT: vfcvt.x.f.v v8, v8
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; RV32-NEXT: ret
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;
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; RV64-i32-LABEL: lrint_nxv2f32:
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; RV64-i32: # %bb.0:
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; RV64-i32-NEXT: vsetvli a0, zero, e32, m1, ta, ma
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; RV64-i32-NEXT: vfcvt.x.f.v v8, v8
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; RV64-i32-NEXT: ret
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;
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; RV64-i64-LABEL: lrint_nxv2f32:
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; RV64-i64: # %bb.0:
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; RV64-i64-NEXT: vsetvli a0, zero, e32, m1, ta, ma
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; RV64-i64-NEXT: vfwcvt.x.f.v v10, v8
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; RV64-i64-NEXT: vmv2r.v v8, v10
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; RV64-i64-NEXT: ret
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%a = call <vscale x 2 x iXLen> @llvm.lrint.nxv2iXLen.nxv2f32(<vscale x 2 x float> %x)
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ret <vscale x 2 x iXLen> %a
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}
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declare <vscale x 2 x iXLen> @llvm.lrint.nxv2iXLen.nxv2f32(<vscale x 2 x float>)
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define <vscale x 4 x iXLen> @lrint_nxv4f32(<vscale x 4 x float> %x) {
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; RV32-LABEL: lrint_nxv4f32:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma
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; RV32-NEXT: vfcvt.x.f.v v8, v8
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; RV32-NEXT: ret
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;
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; RV64-i32-LABEL: lrint_nxv4f32:
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; RV64-i32: # %bb.0:
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; RV64-i32-NEXT: vsetvli a0, zero, e32, m2, ta, ma
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; RV64-i32-NEXT: vfcvt.x.f.v v8, v8
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; RV64-i32-NEXT: ret
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;
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; RV64-i64-LABEL: lrint_nxv4f32:
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; RV64-i64: # %bb.0:
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; RV64-i64-NEXT: vsetvli a0, zero, e32, m2, ta, ma
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; RV64-i64-NEXT: vfwcvt.x.f.v v12, v8
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; RV64-i64-NEXT: vmv4r.v v8, v12
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; RV64-i64-NEXT: ret
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%a = call <vscale x 4 x iXLen> @llvm.lrint.nxv4iXLen.nxv4f32(<vscale x 4 x float> %x)
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ret <vscale x 4 x iXLen> %a
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}
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declare <vscale x 4 x iXLen> @llvm.lrint.nxv4iXLen.nxv4f32(<vscale x 4 x float>)
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define <vscale x 8 x iXLen> @lrint_nxv8f32(<vscale x 8 x float> %x) {
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; RV32-LABEL: lrint_nxv8f32:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetvli a0, zero, e32, m4, ta, ma
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; RV32-NEXT: vfcvt.x.f.v v8, v8
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; RV32-NEXT: ret
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;
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; RV64-i32-LABEL: lrint_nxv8f32:
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; RV64-i32: # %bb.0:
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; RV64-i32-NEXT: vsetvli a0, zero, e32, m4, ta, ma
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; RV64-i32-NEXT: vfcvt.x.f.v v8, v8
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; RV64-i32-NEXT: ret
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;
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; RV64-i64-LABEL: lrint_nxv8f32:
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; RV64-i64: # %bb.0:
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; RV64-i64-NEXT: vsetvli a0, zero, e32, m4, ta, ma
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; RV64-i64-NEXT: vfwcvt.x.f.v v16, v8
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; RV64-i64-NEXT: vmv8r.v v8, v16
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; RV64-i64-NEXT: ret
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%a = call <vscale x 8 x iXLen> @llvm.lrint.nxv8iXLen.nxv8f32(<vscale x 8 x float> %x)
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ret <vscale x 8 x iXLen> %a
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}
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declare <vscale x 8 x iXLen> @llvm.lrint.nxv8iXLen.nxv8f32(<vscale x 8 x float>)
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define <vscale x 16 x iXLen> @lrint_nxv16f32(<vscale x 16 x float> %x) {
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; RV32-LABEL: lrint_nxv16f32:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, ma
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; RV32-NEXT: vfcvt.x.f.v v8, v8
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; RV32-NEXT: ret
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;
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; RV64-i32-LABEL: lrint_nxv16f32:
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; RV64-i32: # %bb.0:
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; RV64-i32-NEXT: vsetvli a0, zero, e32, m8, ta, ma
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; RV64-i32-NEXT: vfcvt.x.f.v v8, v8
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; RV64-i32-NEXT: ret
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;
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; RV64-i64-LABEL: lrint_nxv16f32:
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; RV64-i64: # %bb.0:
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; RV64-i64-NEXT: vsetvli a0, zero, e32, m4, ta, ma
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; RV64-i64-NEXT: vfwcvt.x.f.v v24, v8
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; RV64-i64-NEXT: vfwcvt.x.f.v v16, v12
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; RV64-i64-NEXT: vmv8r.v v8, v24
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; RV64-i64-NEXT: ret
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%a = call <vscale x 16 x iXLen> @llvm.lrint.nxv16iXLen.nxv16f32(<vscale x 16 x float> %x)
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ret <vscale x 16 x iXLen> %a
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}
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declare <vscale x 16 x iXLen> @llvm.lrint.nxv16iXLen.nxv16f32(<vscale x 16 x float>)
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define <vscale x 1 x iXLen> @lrint_nxv1f64(<vscale x 1 x double> %x) {
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; RV32-LABEL: lrint_nxv1f64:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
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; RV32-NEXT: vfncvt.x.f.w v9, v8
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; RV32-NEXT: vmv1r.v v8, v9
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; RV32-NEXT: ret
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;
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; RV64-i32-LABEL: lrint_nxv1f64:
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; RV64-i32: # %bb.0:
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; RV64-i32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
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; RV64-i32-NEXT: vfncvt.x.f.w v9, v8
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; RV64-i32-NEXT: vmv1r.v v8, v9
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; RV64-i32-NEXT: ret
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;
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; RV64-i64-LABEL: lrint_nxv1f64:
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; RV64-i64: # %bb.0:
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; RV64-i64-NEXT: vsetvli a0, zero, e64, m1, ta, ma
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; RV64-i64-NEXT: vfcvt.x.f.v v8, v8
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; RV64-i64-NEXT: ret
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%a = call <vscale x 1 x iXLen> @llvm.lrint.nxv1iXLen.nxv1f64(<vscale x 1 x double> %x)
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ret <vscale x 1 x iXLen> %a
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}
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declare <vscale x 1 x iXLen> @llvm.lrint.nxv1iXLen.nxv1f64(<vscale x 1 x double>)
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define <vscale x 2 x iXLen> @lrint_nxv2f64(<vscale x 2 x double> %x) {
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; RV32-LABEL: lrint_nxv2f64:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, ma
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; RV32-NEXT: vfncvt.x.f.w v10, v8
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; RV32-NEXT: vmv.v.v v8, v10
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; RV32-NEXT: ret
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;
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; RV64-i32-LABEL: lrint_nxv2f64:
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; RV64-i32: # %bb.0:
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; RV64-i32-NEXT: vsetvli a0, zero, e32, m1, ta, ma
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; RV64-i32-NEXT: vfncvt.x.f.w v10, v8
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; RV64-i32-NEXT: vmv.v.v v8, v10
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; RV64-i32-NEXT: ret
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;
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; RV64-i64-LABEL: lrint_nxv2f64:
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; RV64-i64: # %bb.0:
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; RV64-i64-NEXT: vsetvli a0, zero, e64, m2, ta, ma
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; RV64-i64-NEXT: vfcvt.x.f.v v8, v8
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; RV64-i64-NEXT: ret
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%a = call <vscale x 2 x iXLen> @llvm.lrint.nxv2iXLen.nxv2f64(<vscale x 2 x double> %x)
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ret <vscale x 2 x iXLen> %a
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}
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declare <vscale x 2 x iXLen> @llvm.lrint.nxv2iXLen.nxv2f64(<vscale x 2 x double>)
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define <vscale x 4 x iXLen> @lrint_nxv4f64(<vscale x 4 x double> %x) {
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; RV32-LABEL: lrint_nxv4f64:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma
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; RV32-NEXT: vfncvt.x.f.w v12, v8
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; RV32-NEXT: vmv.v.v v8, v12
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; RV32-NEXT: ret
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;
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; RV64-i32-LABEL: lrint_nxv4f64:
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; RV64-i32: # %bb.0:
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; RV64-i32-NEXT: vsetvli a0, zero, e32, m2, ta, ma
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; RV64-i32-NEXT: vfncvt.x.f.w v12, v8
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; RV64-i32-NEXT: vmv.v.v v8, v12
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; RV64-i32-NEXT: ret
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;
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; RV64-i64-LABEL: lrint_nxv4f64:
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; RV64-i64: # %bb.0:
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; RV64-i64-NEXT: vsetvli a0, zero, e64, m4, ta, ma
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; RV64-i64-NEXT: vfcvt.x.f.v v8, v8
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; RV64-i64-NEXT: ret
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%a = call <vscale x 4 x iXLen> @llvm.lrint.nxv4iXLen.nxv4f64(<vscale x 4 x double> %x)
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ret <vscale x 4 x iXLen> %a
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}
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declare <vscale x 4 x iXLen> @llvm.lrint.nxv4iXLen.nxv4f64(<vscale x 4 x double>)
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define <vscale x 8 x iXLen> @lrint_nxv8f64(<vscale x 8 x double> %x) {
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; RV32-LABEL: lrint_nxv8f64:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetvli a0, zero, e32, m4, ta, ma
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; RV32-NEXT: vfncvt.x.f.w v16, v8
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; RV32-NEXT: vmv.v.v v8, v16
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; RV32-NEXT: ret
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;
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; RV64-i32-LABEL: lrint_nxv8f64:
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; RV64-i32: # %bb.0:
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; RV64-i32-NEXT: vsetvli a0, zero, e32, m4, ta, ma
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; RV64-i32-NEXT: vfncvt.x.f.w v16, v8
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; RV64-i32-NEXT: vmv.v.v v8, v16
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; RV64-i32-NEXT: ret
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;
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; RV64-i64-LABEL: lrint_nxv8f64:
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; RV64-i64: # %bb.0:
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; RV64-i64-NEXT: vsetvli a0, zero, e64, m8, ta, ma
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; RV64-i64-NEXT: vfcvt.x.f.v v8, v8
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; RV64-i64-NEXT: ret
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%a = call <vscale x 8 x iXLen> @llvm.lrint.nxv8iXLen.nxv8f64(<vscale x 8 x double> %x)
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ret <vscale x 8 x iXLen> %a
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}
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declare <vscale x 8 x iXLen> @llvm.lrint.nxv8iXLen.nxv8f64(<vscale x 8 x double>)
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