c1a99b2c77
When in 32-bit mode, the backend doesn't currently implement 64-bit atomics, even though the hardware is capable if you have specified a V9 CPU. Thus, limit the width to 32-bit, for now, leaving behind a TODO. This fixes a regression triggered by PR #73176.
67 lines
1.8 KiB
LLVM
67 lines
1.8 KiB
LLVM
; RUN: llc < %s -march=sparc -mcpu=v9 -verify-machineinstrs | FileCheck %s --check-prefixes=SPARC,SPARC32
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; RUN: llc < %s -march=sparcv9 -verify-machineinstrs | FileCheck %s --check-prefixes=SPARC,SPARC64
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; SPARC-LABEL: test_atomic_i64
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; SPARC32: __atomic_load_8
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; SPARC64: ldx [%o0]
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; SPARC64: membar
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; SPARC64: ldx [%o1]
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; SPARC64: membar
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; SPARC64: membar
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; SPARC64: stx {{.+}}, [%o2]
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define i64 @test_atomic_i64(ptr %ptr1, ptr %ptr2, ptr %ptr3) {
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entry:
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%0 = load atomic i64, ptr %ptr1 acquire, align 8
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%1 = load atomic i64, ptr %ptr2 acquire, align 8
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%2 = add i64 %0, %1
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store atomic i64 %2, ptr %ptr3 release, align 8
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ret i64 %2
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}
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; SPARC-LABEL: test_cmpxchg_i64
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; SPARC32: __atomic_compare_exchange_8
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; SPARC64: mov 123, [[R:%[gilo][0-7]]]
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; SPARC64: casx [%o1], %o0, [[R]]
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define i64 @test_cmpxchg_i64(i64 %a, ptr %ptr) {
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entry:
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%pair = cmpxchg ptr %ptr, i64 %a, i64 123 monotonic monotonic
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%b = extractvalue { i64, i1 } %pair, 0
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ret i64 %b
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}
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; SPARC-LABEL: test_swap_i64
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; SPARC32: __atomic_exchange_8
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; SPARC64: casx [%o1],
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define i64 @test_swap_i64(i64 %a, ptr %ptr) {
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entry:
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%b = atomicrmw xchg ptr %ptr, i64 42 monotonic
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ret i64 %b
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}
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; SPARC-LABEL: test_load_sub_64
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; SPARC32: __atomic_fetch_sub_8
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; SPARC64: membar
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; SPARC64: sub
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; SPARC64: casx [%o0]
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; SPARC64: membar
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define zeroext i64 @test_load_sub_64(ptr %p, i64 zeroext %v) {
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entry:
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%0 = atomicrmw sub ptr %p, i64 %v seq_cst
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ret i64 %0
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}
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; SPARC-LABEL: test_load_max_64
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; SPARC32: __atomic_compare_exchange_8
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; SPARC64: membar
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; SPARC64: cmp
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; SPARC64: movg %xcc
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; SPARC64: casx [%o0]
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; SPARC64: membar
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define zeroext i64 @test_load_max_64(ptr %p, i64 zeroext %v) {
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entry:
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%0 = atomicrmw max ptr %p, i64 %v seq_cst
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ret i64 %0
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}
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