b9208aca9b
There are no 64-bit variants of these ALU / SETHI instructions in V9. Remove these instruction definitions and add patterns to match DAG nodes to the generic instructions defined in SparcInstrInfo.td. This is not strictly NFC because of the changes in `2011-01-11-FrameAddr.ll` test. The reason is that Sparc delay slot filler pass handled ADDrr but not ADDXrr, which are now the same instruction.
56 lines
3.4 KiB
LLVM
56 lines
3.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -mtriple=sparcv9-unknown-linux -verify-machineinstrs -stop-after=finalize-isel < %s | FileCheck %s
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; Check that the fp128 load/store is correctly split.
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; The pointer metadata for the upper/lower halves of the load/store should be in
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; sync with the OP address.
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define fp128 @testcase(fp128 %0) {
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; CHECK-LABEL: name: testcase
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; CHECK: bb.0.Entry:
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:qfpregs = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:dfpregs = COPY [[COPY]].sub_odd64
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; CHECK: [[ADDri:%[0-9]+]]:i64regs = ADDri %stack.0, 0
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; CHECK: [[ORri:%[0-9]+]]:i64regs = ORri killed [[ADDri]], 8
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; CHECK: STDFrr [[ORri]], $g0, killed [[COPY1]] :: (store (s64) into %stack.0 + 8)
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; CHECK: [[COPY2:%[0-9]+]]:dfpregs = COPY [[COPY]].sub_even64
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; CHECK: STDFri %stack.0, 0, killed [[COPY2]] :: (store (s64) into %stack.0, align 16)
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; CHECK: [[LDXrr:%[0-9]+]]:i64regs = LDXrr [[ORri]], $g0 :: (load (s64) from %stack.0 + 8)
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; CHECK: [[LDXri:%[0-9]+]]:i64regs = LDXri %stack.0, 0 :: (load (s64) from %stack.0, align 16)
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; CHECK: [[COPY3:%[0-9]+]]:intregs = COPY [[LDXrr]]
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; CHECK: [[COPY4:%[0-9]+]]:intregs = COPY [[LDXri]]
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; CHECK: [[SRLXri:%[0-9]+]]:i64regs = SRLXri [[LDXrr]], 32
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; CHECK: [[COPY5:%[0-9]+]]:intregs = COPY [[SRLXri]]
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; CHECK: [[SRLXri1:%[0-9]+]]:i64regs = SRLXri [[LDXri]], 32
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; CHECK: [[COPY6:%[0-9]+]]:intregs = COPY [[SRLXri1]]
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; CHECK: [[ADDCCri:%[0-9]+]]:intregs = ADDCCri killed [[COPY3]], -1, implicit-def $icc
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; CHECK: [[ADDEri:%[0-9]+]]:intregs = ADDEri killed [[COPY5]], -1, implicit-def $icc, implicit $icc
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; CHECK: [[ADDEri1:%[0-9]+]]:intregs = ADDEri killed [[COPY4]], -1, implicit-def $icc, implicit $icc
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; CHECK: [[ADDEri2:%[0-9]+]]:intregs = ADDEri killed [[COPY6]], -1, implicit-def dead $icc, implicit $icc
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; CHECK: [[SRLri:%[0-9]+]]:i64regs = SRLri killed [[ADDCCri]], 0
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; CHECK: [[COPY7:%[0-9]+]]:i64regs = COPY [[ADDEri]]
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; CHECK: [[SLLXri:%[0-9]+]]:i64regs = SLLXri killed [[COPY7]], 32
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; CHECK: [[ORrr:%[0-9]+]]:i64regs = ORrr killed [[SLLXri]], killed [[SRLri]]
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; CHECK: [[ADDri1:%[0-9]+]]:i64regs = ADDri %stack.1, 0
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; CHECK: [[ORri1:%[0-9]+]]:i64regs = ORri killed [[ADDri1]], 8
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; CHECK: STXrr [[ORri1]], $g0, killed [[ORrr]] :: (store (s64) into %stack.1 + 8, basealign 16)
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; CHECK: [[SRLri1:%[0-9]+]]:i64regs = SRLri killed [[ADDEri1]], 0
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; CHECK: [[COPY8:%[0-9]+]]:i64regs = COPY [[ADDEri2]]
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; CHECK: [[SLLXri1:%[0-9]+]]:i64regs = SLLXri killed [[COPY8]], 32
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; CHECK: [[ORrr1:%[0-9]+]]:i64regs = ORrr killed [[SLLXri1]], killed [[SRLri1]]
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; CHECK: STXri %stack.1, 0, killed [[ORrr1]] :: (store (s64) into %stack.1, align 16)
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; CHECK: [[LDDFri:%[0-9]+]]:dfpregs = LDDFri %stack.1, 0 :: (load (s64) from %stack.1, align 16)
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; CHECK: [[DEF:%[0-9]+]]:qfpregs = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:qfpregs = INSERT_SUBREG [[DEF]], killed [[LDDFri]], %subreg.sub_even64
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; CHECK: [[LDDFrr:%[0-9]+]]:dfpregs = LDDFrr [[ORri1]], $g0 :: (load (s64) from %stack.1 + 8)
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; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:qfpregs = INSERT_SUBREG [[INSERT_SUBREG]], killed [[LDDFrr]], %subreg.sub_odd64
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; CHECK: $q0 = COPY [[INSERT_SUBREG1]]
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; CHECK: RETL 8, implicit $q0
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Entry:
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%1 = bitcast fp128 %0 to i128
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%2 = add i128 %1, -1
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%3 = bitcast i128 %2 to fp128
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ret fp128 %3
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}
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