e8f9a74fbf
This PR adds support for creating leaf functions when there are no CSRs used, no function calls are made, no stack frame is acquired, and contain no try/catch/throw statements. Reviewed By: uweigand Differential Revision: https://reviews.llvm.org/D129687
67 lines
2.0 KiB
LLVM
67 lines
2.0 KiB
LLVM
; RUN: llc < %s -mtriple=s390x-ibm-zos -mcpu=z13 | FileCheck %s
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; CHECK-LABEL: sum_vecs0
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; CHECK: vag 24, 24, 25
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define <2 x i64> @sum_vecs0(<2 x i64> %v1, <2 x i64> %v2) {
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entry:
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%add0 = add <2 x i64> %v1, %v2
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ret <2 x i64> %add0
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}
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; CHECK-LABEL: sum_vecs1
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; CHECK: vaf 1, 24, 25
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; CHECK: vaf 1, 1, 26
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; CHECK: vaf 1, 1, 27
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; CHECK: vaf 1, 1, 28
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; CHECK: vaf 1, 1, 29
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; CHECK: vl 0, 2304(4), 4
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; CHECK: vaf 1, 1, 30
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; CHECK: vaf 1, 1, 31
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; CHECK: vaf 24, 1, 0
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define <4 x i32> @sum_vecs1(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, <4 x i32> %v4, <4 x i32> %v5, <4 x i32> %v6, <4 x i32> %v7, <4 x i32> %v8, <4 x i32> %v9) {
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entry:
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%add0 = add <4 x i32> %v1, %v2
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%add1 = add <4 x i32> %add0, %v3
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%add2 = add <4 x i32> %add1, %v4
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%add3 = add <4 x i32> %add2, %v5
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%add4 = add <4 x i32> %add3, %v6
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%add5 = add <4 x i32> %add4, %v7
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%add6 = add <4 x i32> %add5, %v8
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%add7 = add <4 x i32> %add6, %v9
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ret <4 x i32> %add7
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}
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; Verify that 3 is used for passing integral types if
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; only 24 is used.
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; CHECK-LABEL: call_vecs0
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; CHECK: lgr 3, 1
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define i64 @call_vecs0(i64 %n, <2 x i64> %v1) {
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entry:
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%ret = call i64 (<2 x i64>, i64) @pass_vecs0(<2 x i64> %v1, i64 %n)
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ret i64 %ret
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}
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; Verify that 3 is not allocated for passing integral types
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; if 24 and %f0 are used.
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; CHECK-LABEL: call_vecs1
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; CHECK: vlr 24, 25
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; CHECK: stg 1, 2200(4)
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define i64 @call_vecs1(i64 %n, <2 x i64> %v1, double %x, <2 x i64> %v2) {
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entry:
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%ret = call i64 (<2 x i64>, double, i64) @pass_vecs1(<2 x i64> %v2, double %x, i64 %n)
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ret i64 %ret
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}
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; Verify that 3 is not allocated for passing integral types
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; if 24 and 25 are used.
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; CHECK-LABEL: call_vecs2
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; CHECK: mvghi 2208(4), 55
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define i64 @call_vecs2(<2 x i64> %v1, <2 x i64> %v2) {
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%ret = call i64 (<2 x i64>, <2 x i64>, i64) @pass_vecs2(<2 x i64> %v1, <2 x i64> %v2, i64 55)
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ret i64 %ret
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}
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declare i64 @pass_vecs0(<2 x i64> %v1, i64 %n)
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declare i64 @pass_vecs1(<2 x i64> %v1, double %x, i64 %n)
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declare i64 @pass_vecs2(<2 x i64> %v1, <2 x i64> %v2, i64 %n)
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