a1710eb3cd
The LIT test cases were migrated with the script provided by Nikita Popov. No manual changes were made. Committed without review since no functional changes, after consultation with uweigand.
143 lines
3.8 KiB
LLVM
143 lines
3.8 KiB
LLVM
; Test STOCFHs that are presented as selects.
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; See comments in asm-18.ll about testing high-word operations.
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;
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; RUN: llc < %s -verify-machineinstrs -mtriple=s390x-linux-gnu -mcpu=z13 \
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; RUN: -no-integrated-as | FileCheck %s
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declare void @foo(ptr)
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; Test the simple case, with the loaded value first.
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define void @f1(ptr %ptr, i32 %limit) {
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; CHECK-LABEL: f1:
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; CHECK-DAG: stepa [[REG:%r[0-5]]]
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; CHECK-DAG: clfi %r3, 42
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; CHECK: stocfhhe [[REG]], 0(%r2)
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; CHECK: br %r14
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%alt = call i32 asm "stepa $0", "=h"()
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%cond = icmp ult i32 %limit, 42
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%orig = load i32, ptr %ptr
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%res = select i1 %cond, i32 %orig, i32 %alt
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store i32 %res, ptr %ptr
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ret void
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}
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; ...and with the loaded value second
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define void @f2(ptr %ptr, i32 %limit) {
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; CHECK-LABEL: f2:
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; CHECK-DAG: stepa [[REG:%r[0-5]]]
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; CHECK-DAG: clfi %r3, 42
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; CHECK: stocfhl [[REG]], 0(%r2)
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; CHECK: br %r14
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%alt = call i32 asm "stepa $0", "=h"()
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%cond = icmp ult i32 %limit, 42
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%orig = load i32, ptr %ptr
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%res = select i1 %cond, i32 %alt, i32 %orig
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store i32 %res, ptr %ptr
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ret void
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}
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; Check the high end of the aligned STOC range.
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define void @f3(ptr %base, i32 %limit) {
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; CHECK-LABEL: f3:
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; CHECK-DAG: stepa [[REG:%r[0-5]]]
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; CHECK-DAG: clfi %r3, 42
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; CHECK: stocfhhe [[REG]], 524284(%r2)
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; CHECK: br %r14
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%alt = call i32 asm "stepa $0", "=h"()
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%ptr = getelementptr i32, ptr %base, i64 131071
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%cond = icmp ult i32 %limit, 42
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%orig = load i32, ptr %ptr
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%res = select i1 %cond, i32 %orig, i32 %alt
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store i32 %res, ptr %ptr
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ret void
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}
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; Check the next word up. Other sequences besides this one would be OK.
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define void @f4(ptr %base, i32 %limit) {
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; CHECK-LABEL: f4:
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; CHECK-DAG: stepa [[REG:%r[0-5]]]
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; CHECK-DAG: agfi %r2, 524288
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; CHECK-DAG: clfi %r3, 42
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; CHECK: stocfhhe [[REG]], 0(%r2)
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; CHECK: br %r14
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%alt = call i32 asm "stepa $0", "=h"()
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%ptr = getelementptr i32, ptr %base, i64 131072
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%cond = icmp ult i32 %limit, 42
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%orig = load i32, ptr %ptr
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%res = select i1 %cond, i32 %orig, i32 %alt
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store i32 %res, ptr %ptr
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ret void
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}
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; Check the low end of the STOC range.
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define void @f5(ptr %base, i32 %limit) {
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; CHECK-LABEL: f5:
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; CHECK-DAG: stepa [[REG:%r[0-5]]]
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; CHECK-DAG: clfi %r3, 42
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; CHECK: stocfhhe [[REG]], -524288(%r2)
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; CHECK: br %r14
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%alt = call i32 asm "stepa $0", "=h"()
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%ptr = getelementptr i32, ptr %base, i64 -131072
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%cond = icmp ult i32 %limit, 42
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%orig = load i32, ptr %ptr
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%res = select i1 %cond, i32 %orig, i32 %alt
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store i32 %res, ptr %ptr
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ret void
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}
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; Check the next word down, with the same comments as f8.
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define void @f6(ptr %base, i32 %limit) {
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; CHECK-LABEL: f6:
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; CHECK-DAG: stepa [[REG:%r[0-5]]]
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; CHECK-DAG: agfi %r2, -524292
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; CHECK-DAG: clfi %r3, 42
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; CHECK: stocfhhe [[REG]], 0(%r2)
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; CHECK: br %r14
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%alt = call i32 asm "stepa $0", "=h"()
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%ptr = getelementptr i32, ptr %base, i64 -131073
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%cond = icmp ult i32 %limit, 42
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%orig = load i32, ptr %ptr
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%res = select i1 %cond, i32 %orig, i32 %alt
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store i32 %res, ptr %ptr
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ret void
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}
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; Try a frame index base.
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define void @f7(i32 %limit) {
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; CHECK-LABEL: f7:
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; CHECK: brasl %r14, foo@PLT
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; CHECK: stepa [[REG:%r[0-5]]]
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; CHECK: stocfhhe [[REG]], {{[0-9]+}}(%r15)
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; CHECK: brasl %r14, foo@PLT
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; CHECK: br %r14
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%ptr = alloca i32
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call void @foo(ptr %ptr)
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%alt = call i32 asm "stepa $0", "=h"()
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%cond = icmp ult i32 %limit, 42
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%orig = load i32, ptr %ptr
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%res = select i1 %cond, i32 %orig, i32 %alt
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store i32 %res, ptr %ptr
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call void @foo(ptr %ptr)
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ret void
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}
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; Test that conditionally-executed stores do not use STOC, since STOC
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; is allowed to trap even when the condition is false.
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define void @f8(i32 %a, i32 %b, ptr %dest) {
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; CHECK-LABEL: f8:
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; CHECK-NOT: stoc
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; CHECK: stfh
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; CHECK: br %r14
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entry:
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%val = call i32 asm "stepa $0", "=h"()
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%cmp = icmp ule i32 %a, %b
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br i1 %cmp, label %store, label %exit
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store:
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store i32 %val, ptr %dest
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br label %exit
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exit:
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ret void
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}
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