a65ccc1b9f
On processors supporting vector registers and SIMD instructions, enable i128 as legal type in VRs. This allows many operations to be implemented via native instructions directly in VRs (including add, subtract, logical operations and shifts). For a few other operations (e.g. multiply and divide, as well as atomic operations), we need to move the i128 value back to a GPR pair to use the corresponding instruction there. Overall, this is still beneficial. The patch includes the following LLVM changes: - Enable i128 as legal type - Set up legal operations (in SystemZInstrVector.td) - Custom expansion for i128 add/subtract with carry - Custom expansion for i128 comparisons and selects - Support for moving i128 to/from GPR pairs when required - Handle 128-bit integer constant values everywhere - Use i128 as intrinsic operand type where appropriate - Updated and new test cases In addition, clang builtins are updated to reflect the intrinsic operand type changes (which also improves compatibility with GCC).
113 lines
2.3 KiB
LLVM
113 lines
2.3 KiB
LLVM
; Test floating-point conversion to/from 128-bit integers.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Test signed i128->f128.
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define fp128 @f1(i128 %i) {
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; CHECK-LABEL: f1:
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; CHECK: brasl %r14, __floattitf@PLT
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; CHECK: br %r14
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%conv = sitofp i128 %i to fp128
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ret fp128 %conv
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}
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; Test signed i128->f64.
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define double @f2(i128 %i) {
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; CHECK-LABEL: f2:
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; CHECK: brasl %r14, __floattidf@PLT
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; CHECK: br %r14
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%conv = sitofp i128 %i to double
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ret double %conv
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}
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; Test signed i128->f32.
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define float @f3(i128 %i) {
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; CHECK-LABEL: f3:
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; CHECK: brasl %r14, __floattisf@PLT
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; CHECK: br %r14
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%conv = sitofp i128 %i to float
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ret float %conv
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}
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; Test unsigned i128->f128.
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define fp128 @f4(i128 %i) {
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; CHECK-LABEL: f4:
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; CHECK: brasl %r14, __floatuntitf@PLT
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; CHECK: br %r14
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%conv = uitofp i128 %i to fp128
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ret fp128 %conv
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}
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; Test unsigned i128->f64.
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define double @f5(i128 %i) {
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; CHECK-LABEL: f5:
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; CHECK: brasl %r14, __floatuntidf@PLT
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; CHECK: br %r14
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%conv = uitofp i128 %i to double
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ret double %conv
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}
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; Test unsigned i128->f32.
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define float @f6(i128 %i) {
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; CHECK-LABEL: f6:
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; CHECK: brasl %r14, __floatuntisf@PLT
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; CHECK: br %r14
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%conv = uitofp i128 %i to float
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ret float %conv
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}
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; Test signed f128->i128.
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define i128 @f7(fp128 %f) {
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; CHECK-LABEL: f7:
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; CHECK: brasl %r14, __fixtfti@PLT
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; CHECK: br %r14
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%conv = fptosi fp128 %f to i128
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ret i128 %conv
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}
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; Test signed f64->i128.
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define i128 @f8(double %f) {
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; CHECK-LABEL: f8:
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; CHECK: brasl %r14, __fixdfti@PLT
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; CHECK: br %r14
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%conv = fptosi double %f to i128
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ret i128 %conv
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}
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; Test signed f9->i128.
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define i128 @f9(float %f) {
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; CHECK-LABEL: f9:
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; CHECK: brasl %r14, __fixsfti@PLT
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; CHECK: br %r14
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%conv = fptosi float %f to i128
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ret i128 %conv
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}
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; Test unsigned f128->i128.
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define i128 @f10(fp128 %f) {
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; CHECK-LABEL: f10:
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; CHECK: brasl %r14, __fixunstfti@PLT
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; CHECK: br %r14
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%conv = fptoui fp128 %f to i128
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ret i128 %conv
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}
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; Test unsigned f64->i128.
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define i128 @f11(double %f) {
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; CHECK-LABEL: f11:
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; CHECK: brasl %r14, __fixunsdfti@PLT
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; CHECK: br %r14
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%conv = fptoui double %f to i128
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ret i128 %conv
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}
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; Test unsigned f32->i128.
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define i128 @f12(float %f) {
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; CHECK-LABEL: f12:
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; CHECK: brasl %r14, __fixunssfti@PLT
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; CHECK: br %r14
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%conv = fptoui float %f to i128
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ret i128 %conv
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}
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