a1710eb3cd
The LIT test cases were migrated with the script provided by Nikita Popov. No manual changes were made. Committed without review since no functional changes, after consultation with uweigand.
114 lines
2.6 KiB
LLVM
114 lines
2.6 KiB
LLVM
; Test zero extensions from an i32 to an i64.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Test register extension, starting with an i32.
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define i64 @f1(i32 %a) {
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; CHECK-LABEL: f1:
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; CHECK: llgfr %r2, %r2
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; CHECK: br %r14
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%ext = zext i32 %a to i64
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ret i64 %ext
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}
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; ...and again with an i64.
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define i64 @f2(i64 %a) {
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; CHECK-LABEL: f2:
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; CHECK: llgfr %r2, %r2
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; CHECK: br %r14
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%word = trunc i64 %a to i32
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%ext = zext i32 %word to i64
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ret i64 %ext
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}
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; Check ANDs that are equivalent to zero extension.
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define i64 @f3(i64 %a) {
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; CHECK-LABEL: f3:
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; CHECK: llgfr %r2, %r2
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; CHECK: br %r14
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%ext = and i64 %a, 4294967295
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ret i64 %ext
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}
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; Check LLGF with no displacement.
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define i64 @f4(ptr %src) {
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; CHECK-LABEL: f4:
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; CHECK: llgf %r2, 0(%r2)
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; CHECK: br %r14
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%word = load i32, ptr %src
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%ext = zext i32 %word to i64
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ret i64 %ext
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}
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; Check the high end of the LLGF range.
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define i64 @f5(ptr %src) {
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; CHECK-LABEL: f5:
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; CHECK: llgf %r2, 524284(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32, ptr %src, i64 131071
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%word = load i32, ptr %ptr
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%ext = zext i32 %word to i64
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ret i64 %ext
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}
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f6(ptr %src) {
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; CHECK-LABEL: f6:
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; CHECK: agfi %r2, 524288
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; CHECK: llgf %r2, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32, ptr %src, i64 131072
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%word = load i32, ptr %ptr
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%ext = zext i32 %word to i64
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ret i64 %ext
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}
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; Check the high end of the negative LLGF range.
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define i64 @f7(ptr %src) {
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; CHECK-LABEL: f7:
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; CHECK: llgf %r2, -4(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32, ptr %src, i64 -1
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%word = load i32, ptr %ptr
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%ext = zext i32 %word to i64
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ret i64 %ext
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}
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; Check the low end of the LLGF range.
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define i64 @f8(ptr %src) {
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; CHECK-LABEL: f8:
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; CHECK: llgf %r2, -524288(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32, ptr %src, i64 -131072
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%word = load i32, ptr %ptr
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%ext = zext i32 %word to i64
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ret i64 %ext
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}
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; Check the next word down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f9(ptr %src) {
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; CHECK-LABEL: f9:
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; CHECK: agfi %r2, -524292
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; CHECK: llgf %r2, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32, ptr %src, i64 -131073
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%word = load i32, ptr %ptr
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%ext = zext i32 %word to i64
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ret i64 %ext
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}
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; Check that LLGF allows an index.
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define i64 @f10(i64 %src, i64 %index) {
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; CHECK-LABEL: f10:
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; CHECK: llgf %r2, 524287(%r3,%r2)
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 524287
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%ptr = inttoptr i64 %add2 to ptr
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%word = load i32, ptr %ptr
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%ext = zext i32 %word to i64
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ret i64 %ext
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}
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