a1710eb3cd
The LIT test cases were migrated with the script provided by Nikita Popov. No manual changes were made. Committed without review since no functional changes, after consultation with uweigand.
132 lines
3.4 KiB
LLVM
132 lines
3.4 KiB
LLVM
; Test 32-bit multiplication in which the second operand is a sign-extended
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; i16 memory value.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Check the low end of the MH range.
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define i32 @f1(i32 %lhs, ptr %src) {
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; CHECK-LABEL: f1:
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; CHECK: mh %r2, 0(%r3)
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; CHECK: br %r14
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%half = load i16, ptr %src
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%rhs = sext i16 %half to i32
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%res = mul i32 %lhs, %rhs
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ret i32 %res
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}
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; Check the high end of the aligned MH range.
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define i32 @f2(i32 %lhs, ptr %src) {
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; CHECK-LABEL: f2:
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; CHECK: mh %r2, 4094(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i16, ptr %src, i64 2047
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%half = load i16, ptr %ptr
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%rhs = sext i16 %half to i32
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%res = mul i32 %lhs, %rhs
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ret i32 %res
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}
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; Check the next halfword up, which should use MHY instead of MH.
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define i32 @f3(i32 %lhs, ptr %src) {
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; CHECK-LABEL: f3:
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; CHECK: mhy %r2, 4096(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i16, ptr %src, i64 2048
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%half = load i16, ptr %ptr
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%rhs = sext i16 %half to i32
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%res = mul i32 %lhs, %rhs
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ret i32 %res
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}
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; Check the high end of the aligned MHY range.
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define i32 @f4(i32 %lhs, ptr %src) {
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; CHECK-LABEL: f4:
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; CHECK: mhy %r2, 524286(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i16, ptr %src, i64 262143
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%half = load i16, ptr %ptr
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%rhs = sext i16 %half to i32
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%res = mul i32 %lhs, %rhs
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ret i32 %res
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}
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; Check the next halfword up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i32 @f5(i32 %lhs, ptr %src) {
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; CHECK-LABEL: f5:
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; CHECK: agfi %r3, 524288
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; CHECK: mh %r2, 0(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i16, ptr %src, i64 262144
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%half = load i16, ptr %ptr
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%rhs = sext i16 %half to i32
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%res = mul i32 %lhs, %rhs
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ret i32 %res
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}
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; Check the high end of the negative aligned MHY range.
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define i32 @f6(i32 %lhs, ptr %src) {
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; CHECK-LABEL: f6:
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; CHECK: mhy %r2, -2(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i16, ptr %src, i64 -1
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%half = load i16, ptr %ptr
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%rhs = sext i16 %half to i32
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%res = mul i32 %lhs, %rhs
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ret i32 %res
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}
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; Check the low end of the MHY range.
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define i32 @f7(i32 %lhs, ptr %src) {
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; CHECK-LABEL: f7:
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; CHECK: mhy %r2, -524288(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i16, ptr %src, i64 -262144
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%half = load i16, ptr %ptr
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%rhs = sext i16 %half to i32
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%res = mul i32 %lhs, %rhs
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ret i32 %res
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}
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; Check the next halfword down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i32 @f8(i32 %lhs, ptr %src) {
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; CHECK-LABEL: f8:
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; CHECK: agfi %r3, -524290
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; CHECK: mh %r2, 0(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i16, ptr %src, i64 -262145
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%half = load i16, ptr %ptr
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%rhs = sext i16 %half to i32
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%res = mul i32 %lhs, %rhs
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ret i32 %res
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}
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; Check that MH allows an index.
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define i32 @f9(i32 %lhs, i64 %src, i64 %index) {
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; CHECK-LABEL: f9:
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; CHECK: mh %r2, 4094({{%r4,%r3|%r3,%r4}})
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 4094
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%ptr = inttoptr i64 %add2 to ptr
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%half = load i16, ptr %ptr
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%rhs = sext i16 %half to i32
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%res = mul i32 %lhs, %rhs
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ret i32 %res
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}
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; Check that MHY allows an index.
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define i32 @f10(i32 %lhs, i64 %src, i64 %index) {
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; CHECK-LABEL: f10:
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; CHECK: mhy %r2, 4096({{%r4,%r3|%r3,%r4}})
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 4096
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%ptr = inttoptr i64 %add2 to ptr
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%half = load i16, ptr %ptr
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%rhs = sext i16 %half to i32
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%res = mul i32 %lhs, %rhs
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ret i32 %res
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}
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