a65ccc1b9f
On processors supporting vector registers and SIMD instructions, enable i128 as legal type in VRs. This allows many operations to be implemented via native instructions directly in VRs (including add, subtract, logical operations and shifts). For a few other operations (e.g. multiply and divide, as well as atomic operations), we need to move the i128 value back to a GPR pair to use the corresponding instruction there. Overall, this is still beneficial. The patch includes the following LLVM changes: - Enable i128 as legal type - Set up legal operations (in SystemZInstrVector.td) - Custom expansion for i128 add/subtract with carry - Custom expansion for i128 comparisons and selects - Support for moving i128 to/from GPR pairs when required - Handle 128-bit integer constant values everywhere - Use i128 as intrinsic operand type where appropriate - Updated and new test cases In addition, clang builtins are updated to reflect the intrinsic operand type changes (which also improves compatibility with GCC).
87 lines
1.8 KiB
LLVM
87 lines
1.8 KiB
LLVM
; Test the Test Data Class instruction logic operation conversion from
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; signbit extraction.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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;
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; Extract sign bit.
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define i32 @f1(float %x) {
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; CHECK-LABEL: f1
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; CHECK: tceb %f0, 1365
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%cast = bitcast float %x to i32
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%res = icmp slt i32 %cast, 0
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%xres = zext i1 %res to i32
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ret i32 %xres
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}
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; Extract negated sign bit.
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define i32 @f2(float %x) {
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; CHECK-LABEL: f2
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; CHECK: tceb %f0, 2730
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%cast = bitcast float %x to i32
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%res = icmp sgt i32 %cast, -1
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%xres = zext i1 %res to i32
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ret i32 %xres
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}
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; Extract sign bit.
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define i32 @f3(double %x) {
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; CHECK-LABEL: f3
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; CHECK: tcdb %f0, 1365
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%cast = bitcast double %x to i64
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%res = icmp slt i64 %cast, 0
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%xres = zext i1 %res to i32
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ret i32 %xres
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}
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; Extract negated sign bit.
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define i32 @f4(double %x) {
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; CHECK-LABEL: f4
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; CHECK: tcdb %f0, 2730
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%cast = bitcast double %x to i64
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%res = icmp sgt i64 %cast, -1
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%xres = zext i1 %res to i32
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ret i32 %xres
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}
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; Extract sign bit.
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define i32 @f5(fp128 %x) {
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; CHECK-LABEL: f5
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; CHECK: tcxb %f0, 1365
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%cast = bitcast fp128 %x to i128
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%res = icmp slt i128 %cast, 0
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%xres = zext i1 %res to i32
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ret i32 %xres
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}
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; Extract negated sign bit.
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define i32 @f6(fp128 %x) {
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; CHECK-LABEL: f6
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; CHECK: tcxb %f0, 2730
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%cast = bitcast fp128 %x to i128
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%res = icmp sgt i128 %cast, -1
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%xres = zext i1 %res to i32
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ret i32 %xres
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}
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; Wrong const.
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define i32 @f7(float %x) {
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; CHECK-LABEL: f7
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; CHECK-NOT: tceb
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%cast = bitcast float %x to i32
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%res = icmp slt i32 %cast, -1
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%xres = zext i1 %res to i32
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ret i32 %xres
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}
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; Wrong pred.
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define i32 @f8(float %x) {
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; CHECK-LABEL: f8
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; CHECK-NOT: tceb
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%cast = bitcast float %x to i32
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%res = icmp eq i32 %cast, 0
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%xres = zext i1 %res to i32
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ret i32 %xres
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}
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