a1710eb3cd
The LIT test cases were migrated with the script provided by Nikita Popov. No manual changes were made. Committed without review since no functional changes, after consultation with uweigand.
156 lines
5.5 KiB
LLVM
156 lines
5.5 KiB
LLVM
; Test various target-specific DAG combiner patterns.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Check that an extraction followed by a truncation is effectively treated
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; as a bitcast.
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define void @f1(<4 x i32> %v1, <4 x i32> %v2, ptr %ptr1, ptr %ptr2) {
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; CHECK-LABEL: f1:
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; CHECK: vaf [[REG:%v[0-9]+]], %v24, %v26
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; CHECK-DAG: vsteb [[REG]], 0(%r2), 3
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; CHECK-DAG: vsteb [[REG]], 0(%r3), 15
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; CHECK: br %r14
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%add = add <4 x i32> %v1, %v2
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%elem1 = extractelement <4 x i32> %add, i32 0
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%elem2 = extractelement <4 x i32> %add, i32 3
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%trunc1 = trunc i32 %elem1 to i8
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%trunc2 = trunc i32 %elem2 to i8
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store i8 %trunc1, ptr %ptr1
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store i8 %trunc2, ptr %ptr2
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ret void
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}
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; Test a case where a pack-type shuffle can be eliminated.
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define i16 @f2(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {
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; CHECK-LABEL: f2:
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; CHECK-NOT: vpk
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; CHECK-DAG: vaf [[REG1:%v[0-9]+]], %v24, %v26
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; CHECK-DAG: vaf [[REG2:%v[0-9]+]], %v26, %v28
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; CHECK-DAG: vlgvh {{%r[0-5]}}, [[REG1]], 3
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; CHECK-DAG: vlgvh {{%r[0-5]}}, [[REG2]], 7
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; CHECK: br %r14
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%add1 = add <4 x i32> %v1, %v2
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%add2 = add <4 x i32> %v2, %v3
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%shuffle = shufflevector <4 x i32> %add1, <4 x i32> %add2,
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<4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%bitcast = bitcast <4 x i32> %shuffle to <8 x i16>
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%elem1 = extractelement <8 x i16> %bitcast, i32 1
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%elem2 = extractelement <8 x i16> %bitcast, i32 7
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%res = add i16 %elem1, %elem2
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ret i16 %res
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}
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; ...and again in a case where there's also a splat and a bitcast.
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define i16 @f3(<4 x i32> %v1, <4 x i32> %v2, <2 x i64> %v3) {
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; CHECK-LABEL: f3:
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; CHECK-NOT: vrepg
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; CHECK-NOT: vpk
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; CHECK-DAG: vaf [[REG:%v[0-9]+]], %v24, %v26
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; CHECK-DAG: vlgvh {{%r[0-5]}}, [[REG]], 6
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; CHECK-DAG: vlgvh {{%r[0-5]}}, %v28, 3
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; CHECK: br %r14
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%add = add <4 x i32> %v1, %v2
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%splat = shufflevector <2 x i64> %v3, <2 x i64> undef,
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<2 x i32> <i32 0, i32 0>
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%splatcast = bitcast <2 x i64> %splat to <4 x i32>
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%shuffle = shufflevector <4 x i32> %add, <4 x i32> %splatcast,
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<4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%bitcast = bitcast <4 x i32> %shuffle to <8 x i16>
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%elem1 = extractelement <8 x i16> %bitcast, i32 2
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%elem2 = extractelement <8 x i16> %bitcast, i32 7
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%res = add i16 %elem1, %elem2
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ret i16 %res
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}
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; ...and again with a merge low instead of a pack.
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define i16 @f4(<4 x i32> %v1, <4 x i32> %v2, <2 x i64> %v3) {
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; CHECK-LABEL: f4:
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; CHECK-NOT: vrepg
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; CHECK-NOT: vmr
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; CHECK-DAG: vaf [[REG:%v[0-9]+]], %v24, %v26
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; CHECK-DAG: vlgvh {{%r[0-5]}}, [[REG]], 6
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; CHECK-DAG: vlgvh {{%r[0-5]}}, %v28, 3
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; CHECK: br %r14
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%add = add <4 x i32> %v1, %v2
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%splat = shufflevector <2 x i64> %v3, <2 x i64> undef,
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<2 x i32> <i32 0, i32 0>
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%splatcast = bitcast <2 x i64> %splat to <4 x i32>
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%shuffle = shufflevector <4 x i32> %add, <4 x i32> %splatcast,
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<4 x i32> <i32 2, i32 6, i32 3, i32 7>
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%bitcast = bitcast <4 x i32> %shuffle to <8 x i16>
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%elem1 = extractelement <8 x i16> %bitcast, i32 4
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%elem2 = extractelement <8 x i16> %bitcast, i32 7
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%res = add i16 %elem1, %elem2
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ret i16 %res
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}
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; ...and again with a merge high.
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define i16 @f5(<4 x i32> %v1, <4 x i32> %v2, <2 x i64> %v3) {
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; CHECK-LABEL: f5:
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; CHECK-NOT: vrepg
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; CHECK-NOT: vmr
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; CHECK-DAG: vaf [[REG:%v[0-9]+]], %v24, %v26
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; CHECK-DAG: vlgvh {{%r[0-5]}}, [[REG]], 2
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; CHECK-DAG: vlgvh {{%r[0-5]}}, %v28, 3
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; CHECK: br %r14
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%add = add <4 x i32> %v1, %v2
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%splat = shufflevector <2 x i64> %v3, <2 x i64> undef,
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<2 x i32> <i32 0, i32 0>
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%splatcast = bitcast <2 x i64> %splat to <4 x i32>
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%shuffle = shufflevector <4 x i32> %add, <4 x i32> %splatcast,
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<4 x i32> <i32 0, i32 4, i32 1, i32 5>
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%bitcast = bitcast <4 x i32> %shuffle to <8 x i16>
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%elem1 = extractelement <8 x i16> %bitcast, i32 4
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%elem2 = extractelement <8 x i16> %bitcast, i32 7
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%res = add i16 %elem1, %elem2
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ret i16 %res
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}
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; Test a case where an unpack high can be eliminated from the usual
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; load-extend sequence.
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define void @f6(ptr %ptr1, ptr %ptr2, ptr %ptr3, ptr %ptr4) {
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; CHECK-LABEL: f6:
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; CHECK: vlrepg [[REG:%v[0-9]+]], 0(%r2)
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; CHECK-NOT: vup
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; CHECK-DAG: vsteb [[REG]], 0(%r3), 1
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; CHECK-DAG: vsteb [[REG]], 0(%r4), 2
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; CHECK-DAG: vsteb [[REG]], 0(%r5), 7
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; CHECK: br %r14
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%vec = load <8 x i8>, ptr %ptr1
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%ext = sext <8 x i8> %vec to <8 x i16>
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%elem1 = extractelement <8 x i16> %ext, i32 1
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%elem2 = extractelement <8 x i16> %ext, i32 2
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%elem3 = extractelement <8 x i16> %ext, i32 7
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%trunc1 = trunc i16 %elem1 to i8
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%trunc2 = trunc i16 %elem2 to i8
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%trunc3 = trunc i16 %elem3 to i8
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store i8 %trunc1, ptr %ptr2
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store i8 %trunc2, ptr %ptr3
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store i8 %trunc3, ptr %ptr4
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ret void
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}
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; ...and again with a bitcast inbetween.
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define void @f7(ptr %ptr1, ptr %ptr2, ptr %ptr3, ptr %ptr4) {
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; CHECK-LABEL: f7:
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; CHECK: vlrepf [[REG:%v[0-9]+]], 0(%r2)
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; CHECK-NOT: vup
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; CHECK-DAG: vsteb [[REG]], 0(%r3), 0
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; CHECK-DAG: vsteb [[REG]], 0(%r4), 1
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; CHECK-DAG: vsteb [[REG]], 0(%r5), 3
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; CHECK: br %r14
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%vec = load <4 x i8>, ptr %ptr1
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%ext = sext <4 x i8> %vec to <4 x i32>
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%bitcast = bitcast <4 x i32> %ext to <8 x i16>
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%elem1 = extractelement <8 x i16> %bitcast, i32 1
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%elem2 = extractelement <8 x i16> %bitcast, i32 3
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%elem3 = extractelement <8 x i16> %bitcast, i32 7
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%trunc1 = trunc i16 %elem1 to i8
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%trunc2 = trunc i16 %elem2 to i8
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%trunc3 = trunc i16 %elem3 to i8
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store i8 %trunc1, ptr %ptr2
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store i8 %trunc2, ptr %ptr3
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store i8 %trunc3, ptr %ptr4
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ret void
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}
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