e0919b189b
RegAllocGreedy uses SlotIndexes::getApproxInstrDistance to approximate the length of a live range for its heuristics. Renumbering all slot indexes with the default instruction distance ensures that this estimate will be as accurate as possible, and will not depend on the history of how instructions have been added to and removed from SlotIndexes's maps. This also means that enabling -early-live-intervals, which runs the SlotIndexes analysis earlier, will not cause large amounts of churn due to different register allocator decisions.
365 lines
17 KiB
LLVM
365 lines
17 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve --verify-machineinstrs %s -o - | FileCheck %s
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%struct.arm_2d_size_t = type { i16, i16 }
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define void @__arm_2d_impl_rgb16_colour_filling_with_alpha(ptr noalias nocapture %phwTargetBase, i16 signext %iTargetStride, ptr noalias nocapture readonly %ptCopySize, i16 zeroext %hwColour, i32 %chRatio) {
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; CHECK-LABEL: __arm_2d_impl_rgb16_colour_filling_with_alpha:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: ldrsh.w r12, [r2, #2]
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; CHECK-NEXT: cmp.w r12, #1
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; CHECK-NEXT: it lt
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; CHECK-NEXT: bxlt lr
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; CHECK-NEXT: .LBB0_1: @ %for.cond3.preheader.lr.ph
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; CHECK-NEXT: push {r4, r5, r6, r7, lr}
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; CHECK-NEXT: sub sp, #4
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; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
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; CHECK-NEXT: sub sp, #64
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; CHECK-NEXT: ldrsh.w r7, [r2]
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; CHECK-NEXT: cmp r7, #1
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; CHECK-NEXT: blt.w .LBB0_6
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; CHECK-NEXT: @ %bb.2: @ %for.cond3.preheader.us.preheader
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; CHECK-NEXT: movs r2, #252
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; CHECK-NEXT: ldr r4, [sp, #152]
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; CHECK-NEXT: and.w r6, r2, r3, lsr #3
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; CHECK-NEXT: movs r2, #120
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; CHECK-NEXT: and.w r5, r2, r3, lsr #9
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; CHECK-NEXT: lsls r3, r3, #3
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; CHECK-NEXT: uxtb r3, r3
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; CHECK-NEXT: muls r6, r4, r6
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; CHECK-NEXT: rsb.w r2, r4, #256
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; CHECK-NEXT: vmov.i16 q2, #0xfc
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; CHECK-NEXT: mul lr, r5, r4
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; CHECK-NEXT: vdup.16 q4, r6
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; CHECK-NEXT: mov.w r6, #2016
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; CHECK-NEXT: vmov.i16 q6, #0xf8
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; CHECK-NEXT: mul r5, r3, r4
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; CHECK-NEXT: adds r3, r7, #7
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; CHECK-NEXT: bic r3, r3, #7
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; CHECK-NEXT: vdup.16 q3, lr
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; CHECK-NEXT: subs r3, #8
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; CHECK-NEXT: movs r4, #1
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; CHECK-NEXT: vdup.16 q0, r5
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; CHECK-NEXT: lsls r1, r1, #1
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; CHECK-NEXT: add.w r3, r4, r3, lsr #3
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; CHECK-NEXT: vstrw.32 q0, [sp, #48] @ 16-byte Spill
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; CHECK-NEXT: vmov.i16 q0, #0xf800
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; CHECK-NEXT: movs r4, #0
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; CHECK-NEXT: vdup.16 q5, r6
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; CHECK-NEXT: vmov.i16 q7, #0x78
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; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill
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; CHECK-NEXT: vstrw.32 q2, [sp, #32] @ 16-byte Spill
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; CHECK-NEXT: vstrw.32 q3, [sp, #16] @ 16-byte Spill
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; CHECK-NEXT: .LBB0_3: @ %vector.ph
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; CHECK-NEXT: @ =>This Loop Header: Depth=1
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; CHECK-NEXT: @ Child Loop BB0_4 Depth 2
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; CHECK-NEXT: mov r5, r0
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; CHECK-NEXT: mov r6, r7
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; CHECK-NEXT: dls lr, r3
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; CHECK-NEXT: .LBB0_4: @ %vector.body
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; CHECK-NEXT: @ Parent Loop BB0_3 Depth=1
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; CHECK-NEXT: @ => This Inner Loop Header: Depth=2
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; CHECK-NEXT: vctp.16 r6
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; CHECK-NEXT: subs r6, #8
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vldrht.u16 q0, [r5]
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; CHECK-NEXT: vshr.u16 q1, q0, #3
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; CHECK-NEXT: vand q1, q1, q2
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; CHECK-NEXT: vmov q2, q4
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; CHECK-NEXT: vmla.i16 q2, q1, r2
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; CHECK-NEXT: vshr.u16 q1, q2, #5
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; CHECK-NEXT: vshl.i16 q2, q0, #3
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; CHECK-NEXT: vand q3, q1, q5
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; CHECK-NEXT: vmov q1, q7
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; CHECK-NEXT: vand q2, q2, q6
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; CHECK-NEXT: vmov q7, q6
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; CHECK-NEXT: vmov q6, q5
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; CHECK-NEXT: vmov q5, q4
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; CHECK-NEXT: vldrw.u32 q4, [sp, #48] @ 16-byte Reload
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; CHECK-NEXT: vshr.u16 q0, q0, #9
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; CHECK-NEXT: vmla.i16 q4, q2, r2
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; CHECK-NEXT: vshr.u16 q2, q4, #11
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; CHECK-NEXT: vmov q4, q5
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; CHECK-NEXT: vmov q5, q6
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; CHECK-NEXT: vmov q6, q7
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; CHECK-NEXT: vmov q7, q1
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; CHECK-NEXT: vorr q1, q3, q2
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; CHECK-NEXT: vldrw.u32 q2, [sp, #16] @ 16-byte Reload
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; CHECK-NEXT: vand q0, q0, q7
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; CHECK-NEXT: vmla.i16 q2, q0, r2
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; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload
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; CHECK-NEXT: vand q0, q2, q0
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; CHECK-NEXT: vldrw.u32 q2, [sp, #32] @ 16-byte Reload
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; CHECK-NEXT: vorr q0, q1, q0
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vstrht.16 q0, [r5], #16
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; CHECK-NEXT: le lr, .LBB0_4
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; CHECK-NEXT: @ %bb.5: @ %for.cond3.for.cond.cleanup7_crit_edge.us
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; CHECK-NEXT: @ in Loop: Header=BB0_3 Depth=1
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; CHECK-NEXT: adds r4, #1
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; CHECK-NEXT: add r0, r1
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; CHECK-NEXT: cmp r4, r12
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; CHECK-NEXT: bne .LBB0_3
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; CHECK-NEXT: .LBB0_6:
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; CHECK-NEXT: add sp, #64
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; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
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; CHECK-NEXT: add sp, #4
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; CHECK-NEXT: pop.w {r4, r5, r6, r7, lr}
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; CHECK-NEXT: bx lr
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entry:
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%iHeight = getelementptr inbounds %struct.arm_2d_size_t, ptr %ptCopySize, i32 0, i32 1
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%0 = load i16, ptr %iHeight, align 2
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%conv1 = sext i16 %0 to i32
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%and.i = shl i16 %hwColour, 3
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%shl.i = and i16 %and.i, 248
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%1 = lshr i16 %hwColour, 9
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%shl4.i = and i16 %1, 120
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%2 = lshr i16 %hwColour, 3
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%3 = and i16 %2, 252
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%4 = trunc i32 %chRatio to i16
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%5 = sub i16 256, %4
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%conv30 = sext i16 %iTargetStride to i32
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%cmp61 = icmp sgt i16 %0, 0
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br i1 %cmp61, label %for.cond3.preheader.lr.ph, label %for.cond.cleanup
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for.cond3.preheader.lr.ph: ; preds = %entry
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%6 = load i16, ptr %ptCopySize, align 2
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%conv4 = sext i16 %6 to i32
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%cmp558 = icmp sgt i16 %6, 0
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br i1 %cmp558, label %for.cond3.preheader.us.preheader, label %for.cond.cleanup
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for.cond3.preheader.us.preheader: ; preds = %for.cond3.preheader.lr.ph
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%conv15.us = mul i16 %shl.i, %4
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%conv15.us.1 = mul i16 %3, %4
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%conv15.us.2 = mul i16 %shl4.i, %4
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%n.rnd.up = add nsw i32 %conv4, 7
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%n.vec = and i32 %n.rnd.up, -8
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%broadcast.splatinsert75 = insertelement <8 x i16> poison, i16 %5, i32 0
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%broadcast.splat76 = shufflevector <8 x i16> %broadcast.splatinsert75, <8 x i16> poison, <8 x i32> zeroinitializer
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%broadcast.splatinsert77 = insertelement <8 x i16> poison, i16 %conv15.us, i32 0
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%broadcast.splat78 = shufflevector <8 x i16> %broadcast.splatinsert77, <8 x i16> poison, <8 x i32> zeroinitializer
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%broadcast.splatinsert79 = insertelement <8 x i16> poison, i16 %conv15.us.1, i32 0
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%broadcast.splat80 = shufflevector <8 x i16> %broadcast.splatinsert79, <8 x i16> poison, <8 x i32> zeroinitializer
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%broadcast.splatinsert81 = insertelement <8 x i16> poison, i16 %conv15.us.2, i32 0
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%broadcast.splat82 = shufflevector <8 x i16> %broadcast.splatinsert81, <8 x i16> poison, <8 x i32> zeroinitializer
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br label %vector.ph
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vector.ph: ; preds = %for.cond3.for.cond.cleanup7_crit_edge.us, %for.cond3.preheader.us.preheader
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%phwTargetBase.addr.063.us = phi ptr [ %add.ptr.us, %for.cond3.for.cond.cleanup7_crit_edge.us ], [ %phwTargetBase, %for.cond3.preheader.us.preheader ]
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%y.062.us = phi i32 [ %inc32.us, %for.cond3.for.cond.cleanup7_crit_edge.us ], [ 0, %for.cond3.preheader.us.preheader ]
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br label %vector.body
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vector.body: ; preds = %vector.body, %vector.ph
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%index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
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%next.gep = getelementptr i16, ptr %phwTargetBase.addr.063.us, i32 %index
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%active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %conv4)
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%wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %next.gep, i32 2, <8 x i1> %active.lane.mask, <8 x i16> poison)
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%7 = shl <8 x i16> %wide.masked.load, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
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%8 = and <8 x i16> %7, <i16 248, i16 248, i16 248, i16 248, i16 248, i16 248, i16 248, i16 248>
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%9 = lshr <8 x i16> %wide.masked.load, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>
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%10 = and <8 x i16> %9, <i16 120, i16 120, i16 120, i16 120, i16 120, i16 120, i16 120, i16 120>
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%11 = lshr <8 x i16> %wide.masked.load, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
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%12 = and <8 x i16> %11, <i16 252, i16 252, i16 252, i16 252, i16 252, i16 252, i16 252, i16 252>
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%13 = mul <8 x i16> %8, %broadcast.splat76
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%14 = add <8 x i16> %13, %broadcast.splat78
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%15 = lshr <8 x i16> %14, <i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11>
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%16 = mul <8 x i16> %12, %broadcast.splat76
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%17 = add <8 x i16> %16, %broadcast.splat80
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%18 = mul <8 x i16> %10, %broadcast.splat76
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%19 = add <8 x i16> %18, %broadcast.splat82
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%20 = lshr <8 x i16> %17, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
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%21 = and <8 x i16> %20, <i16 2016, i16 2016, i16 2016, i16 2016, i16 2016, i16 2016, i16 2016, i16 2016>
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%22 = or <8 x i16> %21, %15
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%23 = and <8 x i16> %19, <i16 -2048, i16 -2048, i16 -2048, i16 -2048, i16 -2048, i16 -2048, i16 -2048, i16 -2048>
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%24 = or <8 x i16> %22, %23
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call void @llvm.masked.store.v8i16.p0(<8 x i16> %24, ptr %next.gep, i32 2, <8 x i1> %active.lane.mask)
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%index.next = add i32 %index, 8
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%25 = icmp eq i32 %index.next, %n.vec
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br i1 %25, label %for.cond3.for.cond.cleanup7_crit_edge.us, label %vector.body
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for.cond3.for.cond.cleanup7_crit_edge.us: ; preds = %vector.body
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%add.ptr.us = getelementptr inbounds i16, ptr %phwTargetBase.addr.063.us, i32 %conv30
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%inc32.us = add nuw nsw i32 %y.062.us, 1
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%exitcond66.not = icmp eq i32 %inc32.us, %conv1
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br i1 %exitcond66.not, label %for.cond.cleanup, label %vector.ph
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for.cond.cleanup: ; preds = %for.cond3.for.cond.cleanup7_crit_edge.us, %for.cond3.preheader.lr.ph, %entry
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ret void
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}
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define void @__arm_2d_impl_rgb16_colour_filling_with_alpha_sched(ptr noalias nocapture %phwTargetBase, i16 signext %iTargetStride, ptr noalias nocapture readonly %ptCopySize, i16 zeroext %hwColour, i32 %chRatio) "target-cpu"="cortex-m55" {
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; CHECK-LABEL: __arm_2d_impl_rgb16_colour_filling_with_alpha_sched:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: ldrsh.w r12, [r2, #2]
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; CHECK-NEXT: cmp.w r12, #1
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; CHECK-NEXT: blt.w .LBB1_7
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; CHECK-NEXT: @ %bb.1: @ %for.cond3.preheader.lr.ph
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; CHECK-NEXT: ldrsh.w r2, [r2]
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; CHECK-NEXT: cmp r2, #1
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; CHECK-NEXT: it lt
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; CHECK-NEXT: bxlt lr
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; CHECK-NEXT: .LBB1_2: @ %for.cond3.preheader.us.preheader
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; CHECK-NEXT: push {r4, r5, r6, r7, lr}
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; CHECK-NEXT: sub sp, #4
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; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
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; CHECK-NEXT: sub sp, #80
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; CHECK-NEXT: ldr r7, [sp, #168]
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; CHECK-NEXT: movs r5, #120
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; CHECK-NEXT: lsls r6, r3, #3
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; CHECK-NEXT: movs r4, #252
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; CHECK-NEXT: and.w r5, r5, r3, lsr #9
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; CHECK-NEXT: uxtb r6, r6
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; CHECK-NEXT: and.w r3, r4, r3, lsr #3
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; CHECK-NEXT: muls r6, r7, r6
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; CHECK-NEXT: mul lr, r3, r7
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; CHECK-NEXT: vdup.16 q0, r6
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; CHECK-NEXT: vstrw.32 q0, [sp, #64] @ 16-byte Spill
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; CHECK-NEXT: vdup.16 q0, lr
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; CHECK-NEXT: muls r5, r7, r5
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; CHECK-NEXT: vstrw.32 q0, [sp, #48] @ 16-byte Spill
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; CHECK-NEXT: vmov.i16 q0, #0xfc
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; CHECK-NEXT: mov.w r6, #2016
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; CHECK-NEXT: vstrw.32 q0, [sp, #32] @ 16-byte Spill
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; CHECK-NEXT: vdup.16 q0, r5
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; CHECK-NEXT: rsb.w r3, r7, #256
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; CHECK-NEXT: lsls r7, r1, #1
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; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill
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; CHECK-NEXT: vdup.16 q0, r6
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; CHECK-NEXT: vmov.i16 q2, #0xf8
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; CHECK-NEXT: vmov.i16 q5, #0x78
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; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill
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; CHECK-NEXT: vmov.i16 q6, #0xf800
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; CHECK-NEXT: movs r4, #0
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; CHECK-NEXT: vldrw.u32 q7, [sp] @ 16-byte Reload
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; CHECK-NEXT: .p2align 2
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; CHECK-NEXT: .LBB1_3: @ %vector.ph
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; CHECK-NEXT: @ =>This Loop Header: Depth=1
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; CHECK-NEXT: @ Child Loop BB1_4 Depth 2
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; CHECK-NEXT: mov r5, r0
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; CHECK-NEXT: dlstp.16 lr, r2
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; CHECK-NEXT: .p2align 2
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; CHECK-NEXT: .LBB1_4: @ %vector.body
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; CHECK-NEXT: @ Parent Loop BB1_3 Depth=1
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; CHECK-NEXT: @ => This Inner Loop Header: Depth=2
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; CHECK-NEXT: vldrh.u16 q0, [r5]
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; CHECK-NEXT: vshl.i16 q1, q0, #3
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; CHECK-NEXT: vldrw.u32 q3, [sp, #64] @ 16-byte Reload
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; CHECK-NEXT: vand q1, q1, q2
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; CHECK-NEXT: vmla.i16 q3, q1, r3
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; CHECK-NEXT: vmov.f64 d8, d4
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; CHECK-NEXT: vmov.f64 d9, d5
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; CHECK-NEXT: vldrw.u32 q1, [sp, #32] @ 16-byte Reload
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; CHECK-NEXT: vshr.u16 q2, q0, #9
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; CHECK-NEXT: vshr.u16 q0, q0, #3
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; CHECK-NEXT: vand q0, q0, q1
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; CHECK-NEXT: vldrw.u32 q1, [sp, #48] @ 16-byte Reload
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; CHECK-NEXT: vmla.i16 q1, q0, r3
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; CHECK-NEXT: vand q2, q2, q5
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; CHECK-NEXT: vshr.u16 q0, q3, #11
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; CHECK-NEXT: vldrw.u32 q3, [sp, #16] @ 16-byte Reload
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; CHECK-NEXT: vshr.u16 q1, q1, #5
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; CHECK-NEXT: vmla.i16 q3, q2, r3
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; CHECK-NEXT: vand q1, q1, q7
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; CHECK-NEXT: vorr q0, q1, q0
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; CHECK-NEXT: vand q1, q3, q6
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; CHECK-NEXT: vorr q0, q0, q1
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; CHECK-NEXT: vstrh.16 q0, [r5], #16
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; CHECK-NEXT: vmov.f64 d4, d8
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; CHECK-NEXT: vmov.f64 d5, d9
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; CHECK-NEXT: letp lr, .LBB1_4
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; CHECK-NEXT: @ %bb.5: @ %for.cond3.for.cond.cleanup7_crit_edge.us
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; CHECK-NEXT: @ in Loop: Header=BB1_3 Depth=1
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; CHECK-NEXT: adds r4, #1
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; CHECK-NEXT: add r0, r7
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; CHECK-NEXT: cmp r4, r12
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; CHECK-NEXT: bne .LBB1_3
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; CHECK-NEXT: @ %bb.6:
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; CHECK-NEXT: add sp, #80
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; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
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; CHECK-NEXT: add sp, #4
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; CHECK-NEXT: pop.w {r4, r5, r6, r7, lr}
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; CHECK-NEXT: .LBB1_7: @ %for.cond.cleanup
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; CHECK-NEXT: bx lr
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entry:
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%iHeight = getelementptr inbounds %struct.arm_2d_size_t, ptr %ptCopySize, i32 0, i32 1
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%0 = load i16, ptr %iHeight, align 2
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%conv1 = sext i16 %0 to i32
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%and.i = shl i16 %hwColour, 3
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%shl.i = and i16 %and.i, 248
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%1 = lshr i16 %hwColour, 9
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%shl4.i = and i16 %1, 120
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%2 = lshr i16 %hwColour, 3
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%3 = and i16 %2, 252
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%4 = trunc i32 %chRatio to i16
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%5 = sub i16 256, %4
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%conv30 = sext i16 %iTargetStride to i32
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%cmp61 = icmp sgt i16 %0, 0
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br i1 %cmp61, label %for.cond3.preheader.lr.ph, label %for.cond.cleanup
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for.cond3.preheader.lr.ph: ; preds = %entry
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%6 = load i16, ptr %ptCopySize, align 2
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%conv4 = sext i16 %6 to i32
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%cmp558 = icmp sgt i16 %6, 0
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br i1 %cmp558, label %for.cond3.preheader.us.preheader, label %for.cond.cleanup
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for.cond3.preheader.us.preheader: ; preds = %for.cond3.preheader.lr.ph
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%conv15.us = mul i16 %shl.i, %4
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%conv15.us.1 = mul i16 %3, %4
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%conv15.us.2 = mul i16 %shl4.i, %4
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%n.rnd.up = add nsw i32 %conv4, 7
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%n.vec = and i32 %n.rnd.up, -8
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%broadcast.splatinsert75 = insertelement <8 x i16> poison, i16 %5, i32 0
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%broadcast.splat76 = shufflevector <8 x i16> %broadcast.splatinsert75, <8 x i16> poison, <8 x i32> zeroinitializer
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%broadcast.splatinsert77 = insertelement <8 x i16> poison, i16 %conv15.us, i32 0
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%broadcast.splat78 = shufflevector <8 x i16> %broadcast.splatinsert77, <8 x i16> poison, <8 x i32> zeroinitializer
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%broadcast.splatinsert79 = insertelement <8 x i16> poison, i16 %conv15.us.1, i32 0
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%broadcast.splat80 = shufflevector <8 x i16> %broadcast.splatinsert79, <8 x i16> poison, <8 x i32> zeroinitializer
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%broadcast.splatinsert81 = insertelement <8 x i16> poison, i16 %conv15.us.2, i32 0
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%broadcast.splat82 = shufflevector <8 x i16> %broadcast.splatinsert81, <8 x i16> poison, <8 x i32> zeroinitializer
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br label %vector.ph
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vector.ph: ; preds = %for.cond3.for.cond.cleanup7_crit_edge.us, %for.cond3.preheader.us.preheader
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%phwTargetBase.addr.063.us = phi ptr [ %add.ptr.us, %for.cond3.for.cond.cleanup7_crit_edge.us ], [ %phwTargetBase, %for.cond3.preheader.us.preheader ]
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%y.062.us = phi i32 [ %inc32.us, %for.cond3.for.cond.cleanup7_crit_edge.us ], [ 0, %for.cond3.preheader.us.preheader ]
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br label %vector.body
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vector.body: ; preds = %vector.body, %vector.ph
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%index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
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%next.gep = getelementptr i16, ptr %phwTargetBase.addr.063.us, i32 %index
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%active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %conv4)
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%wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %next.gep, i32 2, <8 x i1> %active.lane.mask, <8 x i16> poison)
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%7 = shl <8 x i16> %wide.masked.load, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
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%8 = and <8 x i16> %7, <i16 248, i16 248, i16 248, i16 248, i16 248, i16 248, i16 248, i16 248>
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%9 = lshr <8 x i16> %wide.masked.load, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>
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%10 = and <8 x i16> %9, <i16 120, i16 120, i16 120, i16 120, i16 120, i16 120, i16 120, i16 120>
|
|
%11 = lshr <8 x i16> %wide.masked.load, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
|
|
%12 = and <8 x i16> %11, <i16 252, i16 252, i16 252, i16 252, i16 252, i16 252, i16 252, i16 252>
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|
%13 = mul <8 x i16> %8, %broadcast.splat76
|
|
%14 = add <8 x i16> %13, %broadcast.splat78
|
|
%15 = lshr <8 x i16> %14, <i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11>
|
|
%16 = mul <8 x i16> %12, %broadcast.splat76
|
|
%17 = add <8 x i16> %16, %broadcast.splat80
|
|
%18 = mul <8 x i16> %10, %broadcast.splat76
|
|
%19 = add <8 x i16> %18, %broadcast.splat82
|
|
%20 = lshr <8 x i16> %17, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
|
|
%21 = and <8 x i16> %20, <i16 2016, i16 2016, i16 2016, i16 2016, i16 2016, i16 2016, i16 2016, i16 2016>
|
|
%22 = or <8 x i16> %21, %15
|
|
%23 = and <8 x i16> %19, <i16 -2048, i16 -2048, i16 -2048, i16 -2048, i16 -2048, i16 -2048, i16 -2048, i16 -2048>
|
|
%24 = or <8 x i16> %22, %23
|
|
call void @llvm.masked.store.v8i16.p0(<8 x i16> %24, ptr %next.gep, i32 2, <8 x i1> %active.lane.mask)
|
|
%index.next = add i32 %index, 8
|
|
%25 = icmp eq i32 %index.next, %n.vec
|
|
br i1 %25, label %for.cond3.for.cond.cleanup7_crit_edge.us, label %vector.body
|
|
|
|
for.cond3.for.cond.cleanup7_crit_edge.us: ; preds = %vector.body
|
|
%add.ptr.us = getelementptr inbounds i16, ptr %phwTargetBase.addr.063.us, i32 %conv30
|
|
%inc32.us = add nuw nsw i32 %y.062.us, 1
|
|
%exitcond66.not = icmp eq i32 %inc32.us, %conv1
|
|
br i1 %exitcond66.not, label %for.cond.cleanup, label %vector.ph
|
|
|
|
for.cond.cleanup: ; preds = %for.cond3.for.cond.cleanup7_crit_edge.us, %for.cond3.preheader.lr.ph, %entry
|
|
ret void
|
|
}
|
|
|
|
declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32) #1
|
|
declare <8 x i16> @llvm.masked.load.v8i16.p0(ptr, i32 immarg, <8 x i1>, <8 x i16>) #2
|
|
declare void @llvm.masked.store.v8i16.p0(<8 x i16>, ptr, i32 immarg, <8 x i1>) #3
|