c2e7c9cb33
In https://github.com/llvm/llvm-project/issues/57452, we found that IRTranslator is translating `i1 true` into `i32 -1`. This is because IRTranslator uses SExt for indices. In this fix, we change the expected behavior of extractelement's index, moving from SExt to ZExt. This change includes both documentation, SelectionDAG and IRTranslator. We also included a test for AMDGPU, updated tests for AArch64, Mips, PowerPC, RISCV, VE, WebAssembly and X86 This patch fixes issue #57452. Differential Revision: https://reviews.llvm.org/D132978
203 lines
5.7 KiB
LLVM
203 lines
5.7 KiB
LLVM
; RUN: llc < %s -mtriple=ve-unknown-unknown -mattr=+vpu | FileCheck %s
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;;; <256 x i64>
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define fastcc i64 @extract_rr_v256i64(i32 signext %idx, <256 x i64> %v) {
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; CHECK-LABEL: extract_rr_v256i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: lvs %s0, %v0(%s0)
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; CHECK-NEXT: b.l.t (, %s10)
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%ret = extractelement <256 x i64> %v, i32 %idx
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ret i64 %ret
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}
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define fastcc i64 @extract_ri7_v256i64(<256 x i64> %v) {
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; CHECK-LABEL: extract_ri7_v256i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lvs %s0, %v0(127)
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; CHECK-NEXT: b.l.t (, %s10)
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%ret = extractelement <256 x i64> %v, i32 127
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ret i64 %ret
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}
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define fastcc i64 @extract_ri8_v256i64(<256 x i64> %v) {
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; CHECK-LABEL: extract_ri8_v256i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvs %s0, %v0(%s0)
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; CHECK-NEXT: b.l.t (, %s10)
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%ret = extractelement <256 x i64> %v, i32 128
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ret i64 %ret
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}
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define fastcc i64 @extract_ri_v512i64(<512 x i64> %v) {
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; CHECK-LABEL: extract_ri_v512i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lvs %s0, %v1(116)
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; CHECK-NEXT: b.l.t (, %s10)
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%ret = extractelement <512 x i64> %v, i32 372
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ret i64 %ret
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}
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;;; <256 x i32>
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define fastcc i32 @extract_rr_v256i32(i32 signext %idx, <256 x i32> %v) {
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; CHECK-LABEL: extract_rr_v256i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: lvs %s0, %v0(%s0)
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; CHECK-NEXT: b.l.t (, %s10)
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%ret = extractelement <256 x i32> %v, i32 %idx
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ret i32 %ret
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}
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define fastcc i32 @extract_ri7_v256i32(<256 x i32> %v) {
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; CHECK-LABEL: extract_ri7_v256i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lvs %s0, %v0(127)
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; CHECK-NEXT: b.l.t (, %s10)
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%ret = extractelement <256 x i32> %v, i32 127
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ret i32 %ret
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}
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define fastcc i32 @extract_ri8_v256i32(<256 x i32> %v) {
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; CHECK-LABEL: extract_ri8_v256i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvs %s0, %v0(%s0)
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; CHECK-NEXT: b.l.t (, %s10)
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%ret = extractelement <256 x i32> %v, i32 128
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ret i32 %ret
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}
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define fastcc i32 @extract_ri_v512i32(<512 x i32> %v) {
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; CHECK-LABEL: extract_ri_v512i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 186
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; CHECK-NEXT: lvs %s0, %v0(%s0)
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; CHECK-NEXT: srl %s0, %s0, 32
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; CHECK-NEXT: b.l.t (, %s10)
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%ret = extractelement <512 x i32> %v, i32 372
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ret i32 %ret
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}
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define fastcc i32 @extract_rr_v512i32(<512 x i32> %v, i32 signext %idx) {
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; CHECK-LABEL: extract_rr_v512i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, -2
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: and %s1, %s0, %s1
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; CHECK-NEXT: srl %s1, %s1, 1
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; CHECK-NEXT: lvs %s1, %v0(%s1)
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; CHECK-NEXT: nnd %s0, %s0, (63)0
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; CHECK-NEXT: sla.w.sx %s0, %s0, 5
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; CHECK-NEXT: srl %s0, %s1, %s0
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: b.l.t (, %s10)
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%ret = extractelement <512 x i32> %v, i32 %idx
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ret i32 %ret
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}
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;;; <256 x double>
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define fastcc double @extract_rr_v256f64(i32 signext %idx, <256 x double> %v) {
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; CHECK-LABEL: extract_rr_v256f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: lvs %s0, %v0(%s0)
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; CHECK-NEXT: b.l.t (, %s10)
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%ret = extractelement <256 x double> %v, i32 %idx
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ret double %ret
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}
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define fastcc double @extract_ri7_v256f64(<256 x double> %v) {
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; CHECK-LABEL: extract_ri7_v256f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lvs %s0, %v0(127)
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; CHECK-NEXT: b.l.t (, %s10)
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%ret = extractelement <256 x double> %v, i32 127
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ret double %ret
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}
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define fastcc double @extract_ri8_v256f64(<256 x double> %v) {
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; CHECK-LABEL: extract_ri8_v256f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvs %s0, %v0(%s0)
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; CHECK-NEXT: b.l.t (, %s10)
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%ret = extractelement <256 x double> %v, i32 128
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ret double %ret
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}
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define fastcc double @extract_ri_v512f64(<512 x double> %v) {
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; CHECK-LABEL: extract_ri_v512f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lvs %s0, %v1(116)
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; CHECK-NEXT: b.l.t (, %s10)
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%ret = extractelement <512 x double> %v, i32 372
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ret double %ret
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}
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;;; <256 x float>
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define fastcc float @extract_rr_v256f32(i32 signext %idx, <256 x float> %v) {
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; CHECK-LABEL: extract_rr_v256f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: lvs %s0, %v0(%s0)
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; CHECK-NEXT: b.l.t (, %s10)
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%ret = extractelement <256 x float> %v, i32 %idx
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ret float %ret
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}
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define fastcc float @extract_ri7_v256f32(<256 x float> %v) {
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; CHECK-LABEL: extract_ri7_v256f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lvs %s0, %v0(127)
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; CHECK-NEXT: b.l.t (, %s10)
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%ret = extractelement <256 x float> %v, i32 127
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ret float %ret
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}
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define fastcc float @extract_ri8_v256f32(<256 x float> %v) {
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; CHECK-LABEL: extract_ri8_v256f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvs %s0, %v0(%s0)
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; CHECK-NEXT: b.l.t (, %s10)
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%ret = extractelement <256 x float> %v, i32 128
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ret float %ret
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}
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define fastcc float @extract_ri_v512f32(<512 x float> %v) {
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; CHECK-LABEL: extract_ri_v512f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 186
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; CHECK-NEXT: lvs %s0, %v0(%s0)
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; CHECK-NEXT: srl %s0, %s0, 32
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; CHECK-NEXT: sll %s0, %s0, 32
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; CHECK-NEXT: b.l.t (, %s10)
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%ret = extractelement <512 x float> %v, i32 372
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ret float %ret
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}
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define fastcc float @extract_rr_v512f32(<512 x float> %v, i32 signext %idx) {
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; CHECK-LABEL: extract_rr_v512f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, -2
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: and %s1, %s0, %s1
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; CHECK-NEXT: srl %s1, %s1, 1
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; CHECK-NEXT: lvs %s1, %v0(%s1)
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; CHECK-NEXT: nnd %s0, %s0, (63)0
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; CHECK-NEXT: sla.w.sx %s0, %s0, 5
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; CHECK-NEXT: srl %s0, %s1, %s0
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: sll %s0, %s0, 32
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; CHECK-NEXT: b.l.t (, %s10)
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%ret = extractelement <512 x float> %v, i32 %idx
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ret float %ret
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}
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