351c10cc72
`+vpu` controls whether VEISelLowering adds any vregs. This defaults to `-vpu` to have scalar code generation out of the box. We bring up vector isel under the `+vpu` flag. Once vector isel is stable we switch to `+vpu` and advertise vregs and vops in TTI. Reviewed By: kaz7 Differential Revision: https://reviews.llvm.org/D90465
6 lines
148 B
LLVM
6 lines
148 B
LLVM
; RUN: llc -march=ve -mattr=help 2>&1 > /dev/null | FileCheck %s
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; CHECK: Available features for this target:
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; CHECK: vpu - Enable the VPU.
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