c2e7c9cb33
In https://github.com/llvm/llvm-project/issues/57452, we found that IRTranslator is translating `i1 true` into `i32 -1`. This is because IRTranslator uses SExt for indices. In this fix, we change the expected behavior of extractelement's index, moving from SExt to ZExt. This change includes both documentation, SelectionDAG and IRTranslator. We also included a test for AMDGPU, updated tests for AArch64, Mips, PowerPC, RISCV, VE, WebAssembly and X86 This patch fixes issue #57452. Differential Revision: https://reviews.llvm.org/D132978
220 lines
6.7 KiB
LLVM
220 lines
6.7 KiB
LLVM
; RUN: llc < %s -mtriple=ve-unknown-unknown -mattr=+vpu | FileCheck %s
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;;; <256 x i64>
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define fastcc <256 x i64> @insert_rr_v256i64(i32 signext %idx, i64 %s) {
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; CHECK-LABEL: insert_rr_v256i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: lsv %v0(%s0), %s1
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; CHECK-NEXT: b.l.t (, %s10)
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%ret = insertelement <256 x i64> undef, i64 %s, i32 %idx
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ret <256 x i64> %ret
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}
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define fastcc <256 x i64> @insert_ri7_v256i64(i64 %s) {
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; CHECK-LABEL: insert_ri7_v256i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lsv %v0(127), %s0
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; CHECK-NEXT: b.l.t (, %s10)
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%ret = insertelement <256 x i64> undef, i64 %s, i32 127
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ret <256 x i64> %ret
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}
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define fastcc <256 x i64> @insert_ri8_v256i64(i64 %s) {
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; CHECK-LABEL: insert_ri8_v256i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 128
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; CHECK-NEXT: lsv %v0(%s1), %s0
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; CHECK-NEXT: b.l.t (, %s10)
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%ret = insertelement <256 x i64> undef, i64 %s, i32 128
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ret <256 x i64> %ret
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}
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define fastcc <512 x i64> @insert_ri_v512i64(i64 %s) {
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; CHECK-LABEL: insert_ri_v512i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lsv %v1(116), %s0
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; CHECK-NEXT: b.l.t (, %s10)
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%ret = insertelement <512 x i64> undef, i64 %s, i32 372
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ret <512 x i64> %ret
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}
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;;; <256 x i32>
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define fastcc <256 x i32> @insert_rr_v256i32(i32 signext %idx, i32 signext %s) {
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; CHECK-LABEL: insert_rr_v256i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: lsv %v0(%s0), %s1
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; CHECK-NEXT: b.l.t (, %s10)
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%ret = insertelement <256 x i32> undef, i32 %s, i32 %idx
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ret <256 x i32> %ret
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}
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define fastcc <256 x i32> @insert_ri7_v256i32(i32 signext %s) {
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; CHECK-LABEL: insert_ri7_v256i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: lsv %v0(127), %s0
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; CHECK-NEXT: b.l.t (, %s10)
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%ret = insertelement <256 x i32> undef, i32 %s, i32 127
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ret <256 x i32> %ret
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}
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define fastcc <256 x i32> @insert_ri8_v256i32(i32 signext %s) {
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; CHECK-LABEL: insert_ri8_v256i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: lea %s1, 128
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; CHECK-NEXT: lsv %v0(%s1), %s0
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; CHECK-NEXT: b.l.t (, %s10)
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%ret = insertelement <256 x i32> undef, i32 %s, i32 128
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ret <256 x i32> %ret
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}
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define fastcc <512 x i32> @insert_ri_v512i32(i32 signext %s) {
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; CHECK-LABEL: insert_ri_v512i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 186
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; CHECK-NEXT: lvs %s2, %v0(%s1)
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; CHECK-NEXT: and %s2, %s2, (32)0
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; CHECK-NEXT: sll %s0, %s0, 32
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; CHECK-NEXT: or %s0, %s2, %s0
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; CHECK-NEXT: lsv %v0(%s1), %s0
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; CHECK-NEXT: b.l.t (, %s10)
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%ret = insertelement <512 x i32> undef, i32 %s, i32 372
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ret <512 x i32> %ret
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}
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define fastcc <512 x i32> @insert_rr_v512i32(i32 signext %idx, i32 signext %s) {
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; CHECK-LABEL: insert_rr_v512i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: nnd %s2, %s0, (63)0
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; CHECK-NEXT: sla.w.sx %s2, %s2, 5
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; CHECK-NEXT: sll %s1, %s1, %s2
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; CHECK-NEXT: lea %s3, -2
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; CHECK-NEXT: and %s3, %s3, (32)0
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; CHECK-NEXT: and %s0, %s0, %s3
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; CHECK-NEXT: srl %s0, %s0, 1
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; CHECK-NEXT: lvs %s3, %v0(%s0)
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; CHECK-NEXT: srl %s2, (32)1, %s2
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; CHECK-NEXT: and %s2, %s3, %s2
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; CHECK-NEXT: or %s1, %s2, %s1
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; CHECK-NEXT: lsv %v0(%s0), %s1
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; CHECK-NEXT: b.l.t (, %s10)
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%ret = insertelement <512 x i32> undef, i32 %s, i32 %idx
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ret <512 x i32> %ret
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}
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;;; <256 x double>
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define fastcc <256 x double> @insert_rr_v256f64(i32 signext %idx, double %s) {
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; CHECK-LABEL: insert_rr_v256f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: lsv %v0(%s0), %s1
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; CHECK-NEXT: b.l.t (, %s10)
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%ret = insertelement <256 x double> undef, double %s, i32 %idx
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ret <256 x double> %ret
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}
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define fastcc <256 x double> @insert_ri7_v256f64(double %s) {
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; CHECK-LABEL: insert_ri7_v256f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lsv %v0(127), %s0
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; CHECK-NEXT: b.l.t (, %s10)
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%ret = insertelement <256 x double> undef, double %s, i32 127
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ret <256 x double> %ret
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}
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define fastcc <256 x double> @insert_ri8_v256f64(double %s) {
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; CHECK-LABEL: insert_ri8_v256f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 128
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; CHECK-NEXT: lsv %v0(%s1), %s0
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; CHECK-NEXT: b.l.t (, %s10)
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%ret = insertelement <256 x double> undef, double %s, i32 128
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ret <256 x double> %ret
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}
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define fastcc <512 x double> @insert_ri_v512f64(double %s) {
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; CHECK-LABEL: insert_ri_v512f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lsv %v1(116), %s0
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; CHECK-NEXT: b.l.t (, %s10)
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%ret = insertelement <512 x double> undef, double %s, i32 372
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ret <512 x double> %ret
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}
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;;; <256 x float>
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define fastcc <256 x float> @insert_rr_v256f32(i32 signext %idx, float %s) {
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; CHECK-LABEL: insert_rr_v256f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: lsv %v0(%s0), %s1
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; CHECK-NEXT: b.l.t (, %s10)
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%ret = insertelement <256 x float> undef, float %s, i32 %idx
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ret <256 x float> %ret
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}
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define fastcc <256 x float> @insert_ri7_v256f32(float %s) {
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; CHECK-LABEL: insert_ri7_v256f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lsv %v0(127), %s0
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; CHECK-NEXT: b.l.t (, %s10)
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%ret = insertelement <256 x float> undef, float %s, i32 127
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ret <256 x float> %ret
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}
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define fastcc <256 x float> @insert_ri8_v256f32(float %s) {
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; CHECK-LABEL: insert_ri8_v256f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 128
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; CHECK-NEXT: lsv %v0(%s1), %s0
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; CHECK-NEXT: b.l.t (, %s10)
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%ret = insertelement <256 x float> undef, float %s, i32 128
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ret <256 x float> %ret
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}
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define fastcc <512 x float> @insert_ri_v512f32(float %s) {
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; CHECK-LABEL: insert_ri_v512f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sra.l %s0, %s0, 32
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; CHECK-NEXT: lea %s1, 186
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; CHECK-NEXT: lvs %s2, %v0(%s1)
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; CHECK-NEXT: and %s2, %s2, (32)0
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; CHECK-NEXT: sll %s0, %s0, 32
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; CHECK-NEXT: or %s0, %s2, %s0
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; CHECK-NEXT: lsv %v0(%s1), %s0
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; CHECK-NEXT: b.l.t (, %s10)
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%ret = insertelement <512 x float> undef, float %s, i32 372
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ret <512 x float> %ret
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}
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define fastcc <512 x float> @insert_rr_v512f32(i32 signext %idx, float %s) {
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; CHECK-LABEL: insert_rr_v512f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sra.l %s1, %s1, 32
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; CHECK-NEXT: lea %s2, -2
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; CHECK-NEXT: and %s2, %s2, (32)0
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; CHECK-NEXT: and %s2, %s0, %s2
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; CHECK-NEXT: srl %s2, %s2, 1
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; CHECK-NEXT: lvs %s3, %v0(%s2)
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; CHECK-NEXT: nnd %s0, %s0, (63)0
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; CHECK-NEXT: sla.w.sx %s0, %s0, 5
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; CHECK-NEXT: srl %s4, (32)1, %s0
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; CHECK-NEXT: and %s3, %s3, %s4
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; CHECK-NEXT: adds.w.zx %s1, %s1, (0)1
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; CHECK-NEXT: sll %s0, %s1, %s0
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; CHECK-NEXT: or %s0, %s3, %s0
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; CHECK-NEXT: lsv %v0(%s2), %s0
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; CHECK-NEXT: b.l.t (, %s10)
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%ret = insertelement <512 x float> undef, float %s, i32 %idx
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ret <512 x float> %ret
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}
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