44a679eaa4
Change the way to truncate i64 to i32 in I64 registers. VE assumed sext values previously. Change it to zext values this time to make it match to the LLVM behaviour. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D92226
132 lines
3.7 KiB
LLVM
132 lines
3.7 KiB
LLVM
; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
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; <256 x i32>
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; Function Attrs: nounwind
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define fastcc <256 x i32> @add_vv_v256i32(<256 x i32> %x, <256 x i32> %y) {
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; CHECK-LABEL: add_vv_v256i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 256
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vadds.w.sx %v0, %v0, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%z = add <256 x i32> %x, %y
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ret <256 x i32> %z
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}
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; Function Attrs: nounwind
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define fastcc <256 x i32> @add_sv_v256i32(i32 %x, <256 x i32> %y) {
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; CHECK-LABEL: add_sv_v256i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: lea %s1, 256
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vadds.w.sx %v0, %s0, %v0
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; CHECK-NEXT: b.l.t (, %s10)
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%xins = insertelement <256 x i32> undef, i32 %x, i32 0
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%vx = shufflevector <256 x i32> %xins, <256 x i32> undef, <256 x i32> zeroinitializer
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%z = add <256 x i32> %vx, %y
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ret <256 x i32> %z
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}
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; Function Attrs: nounwind
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define fastcc <256 x i32> @add_vs_v256i32(<256 x i32> %x, i32 %y) {
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; CHECK-LABEL: add_vs_v256i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: lea %s1, 256
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vadds.w.sx %v0, %s0, %v0
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; CHECK-NEXT: b.l.t (, %s10)
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%yins = insertelement <256 x i32> undef, i32 %y, i32 0
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%vy = shufflevector <256 x i32> %yins, <256 x i32> undef, <256 x i32> zeroinitializer
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%z = add <256 x i32> %x, %vy
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ret <256 x i32> %z
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}
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; <256 x i64>
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; Function Attrs: nounwind
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define fastcc <256 x i64> @add_vv_v256i64(<256 x i64> %x, <256 x i64> %y) {
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; CHECK-LABEL: add_vv_v256i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 256
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vadds.l %v0, %v0, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%z = add <256 x i64> %x, %y
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ret <256 x i64> %z
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}
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; Function Attrs: nounwind
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define fastcc <256 x i64> @add_sv_v256i64(i64 %x, <256 x i64> %y) {
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; CHECK-LABEL: add_sv_v256i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 256
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vadds.l %v0, %s0, %v0
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; CHECK-NEXT: b.l.t (, %s10)
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%xins = insertelement <256 x i64> undef, i64 %x, i32 0
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%vx = shufflevector <256 x i64> %xins, <256 x i64> undef, <256 x i32> zeroinitializer
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%z = add <256 x i64> %vx, %y
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ret <256 x i64> %z
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}
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; Function Attrs: nounwind
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define fastcc <256 x i64> @add_vs_v256i64(<256 x i64> %x, i64 %y) {
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; CHECK-LABEL: add_vs_v256i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 256
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vadds.l %v0, %s0, %v0
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; CHECK-NEXT: b.l.t (, %s10)
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%yins = insertelement <256 x i64> undef, i64 %y, i32 0
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%vy = shufflevector <256 x i64> %yins, <256 x i64> undef, <256 x i32> zeroinitializer
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%z = add <256 x i64> %x, %vy
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ret <256 x i64> %z
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}
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; <128 x i64>
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; We expect this to be widened.
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; Function Attrs: nounwind
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define fastcc <128 x i64> @add_vv_v128i64(<128 x i64> %x, <128 x i64> %y) {
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; CHECK-LABEL: add_vv_v128i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 256
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vadds.l %v0, %v0, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%z = add <128 x i64> %x, %y
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ret <128 x i64> %z
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}
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; <256 x i16>
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; We expect promotion.
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; Function Attrs: nounwind
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define fastcc <256 x i16> @add_vv_v256i16(<256 x i16> %x, <256 x i16> %y) {
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; CHECK-LABEL: add_vv_v256i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 256
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vadds.w.sx %v0, %v0, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%z = add <256 x i16> %x, %y
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ret <256 x i16> %z
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}
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; <128 x i16>
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; We expect this to be scalarized (for now).
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; Function Attrs: nounwind
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define fastcc <128 x i16> @add_vv_v128i16(<128 x i16> %x, <128 x i16> %y) {
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; CHECK-LABEL: add_vv_v128i16:
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; CHECK-NOT: vadd
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%z = add <128 x i16> %x, %y
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ret <128 x i16> %z
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}
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