a983ef2c17
Correct the legality of i32 mul_lohi on AArch64. Previously, AArch64 incorrectly reported i32 mul_lohi as Legal. This allowed BuildUDIV/SDIV to use them. A later DAGCombiner would replace them with MULHS/MULHU because only the high half was used. This conversion does not check the legality of MULHS/MULHU under the assumption that LegalizeDAG can turn it back into MUL_LOHI later. After they are converted to MULHS/MULHU, DAGCombine ran and saw that these operations aren't supported but an i64 MUL is. So they get converted to that plus a shift. Without this, LegalizeDAG would convert back MUL_LOHI and isel would fail to find a pattern. This patch teaches BuildUDIV/SDIV to create the wide mul and shift so that we can report the correct operation legality on AArch64. It also enables div by constant folding for more cases on VE. I don't know if VE wants this div by constant optimization or not. If they don't want it, they can use the isIntDivCheap hook to disable it. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D150333
56 lines
1.9 KiB
LLVM
56 lines
1.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
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; This would assert because VE specified that all setcc
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; nodes (even with vector operands) return a scalar value.
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define <4 x i8> @udiv_by_minus_one(<4 x i8> %x) {
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; CHECK-LABEL: udiv_by_minus_one:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s0, %s0, (56)0
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; CHECK-NEXT: lea %s4, 16843010
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; CHECK-NEXT: muls.l %s0, %s0, %s4
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; CHECK-NEXT: srl %s0, %s0, 32
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; CHECK-NEXT: and %s1, %s1, (56)0
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; CHECK-NEXT: muls.l %s1, %s1, %s4
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; CHECK-NEXT: srl %s1, %s1, 32
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; CHECK-NEXT: and %s2, %s2, (56)0
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; CHECK-NEXT: muls.l %s2, %s2, %s4
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; CHECK-NEXT: srl %s2, %s2, 32
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; CHECK-NEXT: and %s3, %s3, (56)0
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; CHECK-NEXT: muls.l %s3, %s3, %s4
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; CHECK-NEXT: srl %s3, %s3, 32
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; CHECK-NEXT: b.l.t (, %s10)
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%r = udiv <4 x i8> %x, <i8 255, i8 255, i8 255, i8 255>
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ret <4 x i8> %r
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}
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define <4 x i8> @urem_by_minus_one(<4 x i8> %x) {
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; CHECK-LABEL: urem_by_minus_one:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s0, %s0, (56)0
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; CHECK-NEXT: and %s1, %s1, (56)0
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; CHECK-NEXT: and %s2, %s2, (56)0
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; CHECK-NEXT: and %s3, %s3, (56)0
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; CHECK-NEXT: lea %s4, 16843010
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; CHECK-NEXT: muls.l %s5, %s3, %s4
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; CHECK-NEXT: srl %s5, %s5, 32
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; CHECK-NEXT: muls.w.sx %s5, %s5, (56)0
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; CHECK-NEXT: subs.w.sx %s3, %s3, %s5
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; CHECK-NEXT: muls.l %s5, %s2, %s4
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; CHECK-NEXT: srl %s5, %s5, 32
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; CHECK-NEXT: muls.w.sx %s5, %s5, (56)0
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; CHECK-NEXT: subs.w.sx %s2, %s2, %s5
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; CHECK-NEXT: muls.l %s5, %s1, %s4
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; CHECK-NEXT: srl %s5, %s5, 32
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; CHECK-NEXT: muls.w.sx %s5, %s5, (56)0
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; CHECK-NEXT: subs.w.sx %s1, %s1, %s5
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; CHECK-NEXT: muls.l %s4, %s0, %s4
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; CHECK-NEXT: srl %s4, %s4, 32
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; CHECK-NEXT: muls.w.sx %s4, %s4, (56)0
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; CHECK-NEXT: subs.w.sx %s0, %s0, %s4
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; CHECK-NEXT: b.l.t (, %s10)
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%r = urem <4 x i8> %x, <i8 255, i8 255, i8 255, i8 255>
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ret <4 x i8> %r
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}
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