91fad1167a
fneg instruction isel and tests. We do this also in preparation of fused negatate-multiple-add fp operations. Reviewed By: kaz7 Differential Revision: https://reviews.llvm.org/D121620
26 lines
776 B
LLVM
26 lines
776 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
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define fastcc <256 x float> @test_vec_fneg_v256f32_v(<256 x float> %v) {
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; CHECK-LABEL: test_vec_fneg_v256f32_v:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 256
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vxor %v0, (1)1, %v0
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; CHECK-NEXT: b.l.t (, %s10)
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%neg = fneg <256 x float> %v
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ret <256 x float> %neg
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}
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define fastcc <256 x double> @test_vec_fneg_v256f64_v(<256 x double> %v) {
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; CHECK-LABEL: test_vec_fneg_v256f64_v:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 256
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vxor %v0, (1)1, %v0
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; CHECK-NEXT: b.l.t (, %s10)
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%neg = fneg <256 x double> %v
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ret <256 x double> %neg
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}
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