69a322fed1
There are a variety of cases where we want more control over the exact
instruction emitted. This commit creates a new pass to fixup
instructions after the DAG has been lowered. The pass is only meant to
replace instructions that are guranteed to be interchangable, not to
do analysis for special cases.
Handling these instruction changes in in X86ISelLowering of
X86ISelDAGToDAG isn't ideal, as its liable to either break existing
patterns that expected a certain instruction or generate infinite
loops.
As well, operating as the MachineInstruction level allows us to access
scheduling/code size information for making the decisions.
Currently only implements `{v}permilps` -> `{v}shufps/{v}shufd` but
more transforms can be added.
Differential Revision: https://reviews.llvm.org/D143787
129 lines
5.3 KiB
LLVM
129 lines
5.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s
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define <8 x float> @A(<8 x float> %a) nounwind uwtable readnone ssp {
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; CHECK-LABEL: A:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
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; CHECK-NEXT: retq
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%shuffle = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> <i32 8, i32 8, i32 8, i32 8, i32 0, i32 1, i32 2, i32 3>
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ret <8 x float> %shuffle
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}
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define <4 x double> @B(<4 x double> %a) nounwind uwtable readnone ssp {
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; CHECK-LABEL: B:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
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; CHECK-NEXT: retq
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%shuffle = shufflevector <4 x double> %a, <4 x double> undef, <4 x i32> <i32 4, i32 4, i32 0, i32 1>
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ret <4 x double> %shuffle
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}
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declare <2 x double> @llvm.x86.sse2.min.pd(<2 x double>, <2 x double>) nounwind readnone
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declare <2 x double> @llvm.x86.sse2.min.sd(<2 x double>, <2 x double>) nounwind readnone
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define void @insert_crash() nounwind {
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; CHECK-LABEL: insert_crash:
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; CHECK: # %bb.0: # %allocas
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; CHECK-NEXT: vxorpd %xmm0, %xmm0, %xmm0
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; CHECK-NEXT: vminpd %xmm0, %xmm0, %xmm0
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; CHECK-NEXT: vminsd %xmm0, %xmm0, %xmm0
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; CHECK-NEXT: vcvtsd2ss %xmm0, %xmm0, %xmm0
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; CHECK-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0,0,0]
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; CHECK-NEXT: vmovups %xmm0, (%rax)
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; CHECK-NEXT: retq
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allocas:
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%v1.i.i451 = shufflevector <4 x double> zeroinitializer, <4 x double> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
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%ret_0a.i.i.i452 = shufflevector <4 x double> %v1.i.i451, <4 x double> undef, <2 x i32> <i32 0, i32 1>
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%vret_0.i.i.i454 = tail call <2 x double> @llvm.x86.sse2.min.pd(<2 x double> %ret_0a.i.i.i452, <2 x double> undef) nounwind
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%ret_val.i.i.i463 = tail call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> %vret_0.i.i.i454, <2 x double> undef) nounwind
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%ret.i1.i.i464 = extractelement <2 x double> %ret_val.i.i.i463, i32 0
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%double2float = fptrunc double %ret.i1.i.i464 to float
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%smearinsert50 = insertelement <4 x float> undef, float %double2float, i32 3
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%blendAsInt.i503 = bitcast <4 x float> %smearinsert50 to <4 x i32>
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store <4 x i32> %blendAsInt.i503, ptr undef, align 4
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ret void
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}
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;; DAG Combine must remove useless vinsertf128 instructions
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define <4 x i32> @DAGCombineA(<4 x i32> %v1) nounwind readonly {
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; CHECK-LABEL: DAGCombineA:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%t1 = shufflevector <4 x i32> %v1, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%t2 = shufflevector <8 x i32> %t1, <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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ret <4 x i32> %t2
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}
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define <8 x i32> @DAGCombineB(<8 x i32> %v1, <8 x i32> %v2) nounwind readonly {
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; CHECK-LABEL: DAGCombineB:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpaddd %xmm1, %xmm0, %xmm2
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; CHECK-NEXT: vextractf128 $1, %ymm1, %xmm1
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; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm3
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; CHECK-NEXT: vpaddd %xmm1, %xmm3, %xmm1
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; CHECK-NEXT: vpaddd %xmm3, %xmm1, %xmm1
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; CHECK-NEXT: vpaddd %xmm0, %xmm2, %xmm0
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; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; CHECK-NEXT: retq
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%t1 = add <8 x i32> %v1, %v2
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%t2 = add <8 x i32> %t1, %v1
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ret <8 x i32> %t2
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}
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define <4 x double> @insert_undef_pd(<4 x double> %a0, <2 x double> %a1) {
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; CHECK-LABEL: insert_undef_pd:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmovaps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%res = call <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double> undef, <2 x double> %a1, i8 0)
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ret <4 x double> %res
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}
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declare <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double>, <2 x double>, i8) nounwind readnone
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define <8 x float> @insert_undef_ps(<8 x float> %a0, <4 x float> %a1) {
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; CHECK-LABEL: insert_undef_ps:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmovaps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%res = call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> undef, <4 x float> %a1, i8 0)
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ret <8 x float> %res
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}
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declare <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float>, <4 x float>, i8) nounwind readnone
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define <8 x i32> @insert_undef_si(<8 x i32> %a0, <4 x i32> %a1) {
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; CHECK-LABEL: insert_undef_si:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmovaps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%res = call <8 x i32> @llvm.x86.avx.vinsertf128.si.256(<8 x i32> undef, <4 x i32> %a1, i8 0)
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ret <8 x i32> %res
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}
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declare <8 x i32> @llvm.x86.avx.vinsertf128.si.256(<8 x i32>, <4 x i32>, i8) nounwind readnone
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; rdar://10643481
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define <8 x float> @vinsertf128_combine(ptr nocapture %f) nounwind uwtable readonly ssp {
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; CHECK-LABEL: vinsertf128_combine:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vinsertf128 $1, 16(%rdi), %ymm0, %ymm0
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; CHECK-NEXT: retq
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%add.ptr = getelementptr inbounds float, ptr %f, i64 4
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%t1 = load <4 x float>, ptr %add.ptr, align 16
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%t2 = tail call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> undef, <4 x float> %t1, i8 1)
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ret <8 x float> %t2
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}
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; rdar://11076953
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define <8 x float> @vinsertf128_ucombine(ptr nocapture %f) nounwind uwtable readonly ssp {
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; CHECK-LABEL: vinsertf128_ucombine:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vinsertf128 $1, 16(%rdi), %ymm0, %ymm0
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; CHECK-NEXT: retq
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%add.ptr = getelementptr inbounds float, ptr %f, i64 4
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%t1 = load <4 x float>, ptr %add.ptr, align 8
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%t2 = tail call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> undef, <4 x float> %t1, i8 1)
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ret <8 x float> %t2
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}
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