0aef747b84
The motivation is that the update script has at least two deviations (`<...>@GOT`/`<...>@PLT`/ and not hiding pointer arithmetics) from what pretty much all the checklines were generated with, and most of the tests are still not updated, so each time one of the non-up-to-date tests is updated to see the effect of the code change, there is a lot of noise. Instead of having to deal with that each time, let's just deal with everything at once. This has been done via: ``` cd llvm-project/llvm/test/CodeGen/X86 grep -rl "; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py" | xargs -L1 <...>/llvm-project/llvm/utils/update_llc_test_checks.py --llc-binary <...>/llvm-project/build/bin/llc ``` Not all tests were regenerated, however.
208 lines
6.4 KiB
LLVM
208 lines
6.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -O2 -mtriple=x86_64-linux-android -mattr=+mmx \
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; RUN: -enable-legalize-types-checking | FileCheck %s
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; RUN: llc < %s -O2 -mtriple=x86_64-linux-gnu -mattr=+mmx \
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; RUN: -enable-legalize-types-checking | FileCheck %s
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define i32 @TestComp128GT(fp128 %d1, fp128 %d2) {
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; CHECK-LABEL: TestComp128GT:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushq %rax
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: callq __gttf2@PLT
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; CHECK-NEXT: xorl %ecx, %ecx
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; CHECK-NEXT: testl %eax, %eax
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; CHECK-NEXT: setg %cl
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; CHECK-NEXT: movl %ecx, %eax
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; CHECK-NEXT: popq %rcx
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: retq
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entry:
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%cmp = fcmp ogt fp128 %d1, %d2
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @TestComp128GE(fp128 %d1, fp128 %d2) {
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; CHECK-LABEL: TestComp128GE:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushq %rax
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: callq __getf2@PLT
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; CHECK-NEXT: xorl %ecx, %ecx
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; CHECK-NEXT: testl %eax, %eax
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; CHECK-NEXT: setns %cl
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; CHECK-NEXT: movl %ecx, %eax
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; CHECK-NEXT: popq %rcx
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: retq
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entry:
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%cmp = fcmp oge fp128 %d1, %d2
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @TestComp128LT(fp128 %d1, fp128 %d2) {
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; CHECK-LABEL: TestComp128LT:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushq %rax
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: callq __lttf2@PLT
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; CHECK-NEXT: xorl %ecx, %ecx
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; CHECK-NEXT: testl %eax, %eax
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; CHECK-NEXT: sets %cl
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; CHECK-NEXT: movl %ecx, %eax
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; CHECK-NEXT: popq %rcx
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: retq
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entry:
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%cmp = fcmp olt fp128 %d1, %d2
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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; FIXME: This used to generate a shrl to move the sign bit of eax into bit 0.
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; This no longer happens with fp128 compares being expanded by LegalizeDAG.
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; We can add a new DAG combine for X86ISD::CMP/SETCC to restore this.
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}
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define i32 @TestComp128LE(fp128 %d1, fp128 %d2) {
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; CHECK-LABEL: TestComp128LE:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushq %rax
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: callq __letf2@PLT
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; CHECK-NEXT: xorl %ecx, %ecx
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; CHECK-NEXT: testl %eax, %eax
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; CHECK-NEXT: setle %cl
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; CHECK-NEXT: movl %ecx, %eax
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; CHECK-NEXT: popq %rcx
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: retq
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entry:
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%cmp = fcmp ole fp128 %d1, %d2
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @TestComp128EQ(fp128 %d1, fp128 %d2) {
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; CHECK-LABEL: TestComp128EQ:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushq %rax
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: callq __eqtf2@PLT
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; CHECK-NEXT: xorl %ecx, %ecx
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; CHECK-NEXT: testl %eax, %eax
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; CHECK-NEXT: sete %cl
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; CHECK-NEXT: movl %ecx, %eax
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; CHECK-NEXT: popq %rcx
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: retq
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entry:
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%cmp = fcmp oeq fp128 %d1, %d2
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @TestComp128NE(fp128 %d1, fp128 %d2) {
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; CHECK-LABEL: TestComp128NE:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushq %rax
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: callq __netf2@PLT
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; CHECK-NEXT: xorl %ecx, %ecx
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; CHECK-NEXT: testl %eax, %eax
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; CHECK-NEXT: setne %cl
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; CHECK-NEXT: movl %ecx, %eax
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; CHECK-NEXT: popq %rcx
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: retq
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entry:
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%cmp = fcmp une fp128 %d1, %d2
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @TestComp128UEQ(fp128 %d1, fp128 %d2) {
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; CHECK-LABEL: TestComp128UEQ:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: subq $32, %rsp
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: .cfi_offset %rbx, -16
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; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
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; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
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; CHECK-NEXT: callq __eqtf2@PLT
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; CHECK-NEXT: testl %eax, %eax
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; CHECK-NEXT: sete %bl
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; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
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; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
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; CHECK-NEXT: callq __unordtf2@PLT
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; CHECK-NEXT: testl %eax, %eax
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; CHECK-NEXT: setne %al
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; CHECK-NEXT: orb %bl, %al
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; CHECK-NEXT: movzbl %al, %eax
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; CHECK-NEXT: addq $32, %rsp
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: retq
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entry:
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%cmp = fcmp ueq fp128 %d1, %d2
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @TestComp128ONE(fp128 %d1, fp128 %d2) {
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; CHECK-LABEL: TestComp128ONE:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: subq $32, %rsp
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: .cfi_offset %rbx, -16
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; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
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; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
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; CHECK-NEXT: callq __eqtf2@PLT
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; CHECK-NEXT: testl %eax, %eax
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; CHECK-NEXT: setne %bl
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; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
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; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
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; CHECK-NEXT: callq __unordtf2@PLT
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; CHECK-NEXT: testl %eax, %eax
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: andb %bl, %al
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; CHECK-NEXT: movzbl %al, %eax
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; CHECK-NEXT: addq $32, %rsp
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: retq
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entry:
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%cmp = fcmp one fp128 %d1, %d2
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define fp128 @TestMax(fp128 %x, fp128 %y) {
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; CHECK-LABEL: TestMax:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: subq $40, %rsp
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
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; CHECK-NEXT: movaps %xmm1, (%rsp) # 16-byte Spill
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; CHECK-NEXT: callq __gttf2@PLT
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; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
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; CHECK-NEXT: testl %eax, %eax
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; CHECK-NEXT: jg .LBB8_2
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; CHECK-NEXT: # %bb.1: # %entry
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; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
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; CHECK-NEXT: .LBB8_2: # %entry
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; CHECK-NEXT: addq $40, %rsp
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: retq
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entry:
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%cmp = fcmp ogt fp128 %x, %y
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%cond = select i1 %cmp, fp128 %x, fp128 %y
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ret fp128 %cond
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}
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