86eff6be68
This change adjusts the cost modeling used when the target does not have a schedule model with individual instruction latencies. After this change, we use the default latency information available from TargetSchedule. The default latency information essentially ends up treating most instructions as latency 1, with a few "expensive" ones getting a higher cost. Previously, we unconditionally applied the first legal pattern - without any consideration of profitability. As a result, this change both prevents some patterns being applied, and changes which patterns are exercised. (i.e. previously the first pattern was applied, afterwards, maybe the second one is because the first wasn't profitable.) The motivation here is two fold. First, this brings the default behavior in line with the behavior when -mcpu or -mtune is specified. This improves test coverage, and generally makes it less likely we will have bad surprises when providing more information to the compiler. Second, this enables some reassociation for ILP by default. Despite being unconditionally enabled, the prior code tended to "reassociate" repeatedly through an entire chain and simply moving the first operand to the end. The result was still a serial chain, just a different one. With this change, one of the intermediate transforms is unprofitable and we end up with a partially flattened tree. Note that the resulting code diffs show significant room for improvement in the basic algorithm. I am intentionally excluding those from this patch. For the test diffs, I don't seen any concerning regressions. I took a fairly close look at the RISCV ones, but only skimmed the x86 (particularly vector x86) changes. Differential Revision: https://reviews.llvm.org/D141017
122 lines
4.0 KiB
LLVM
122 lines
4.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -stack-symbol-ordering=0 -tailcallopt -code-model=medium -mtriple=i686-linux-gnu -mcpu=pentium | FileCheck %s
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; Check the HiPE calling convention works (x86-32)
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define void @zap(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: zap:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushl %ebp
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; CHECK-NEXT: pushl %ebx
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; CHECK-NEXT: pushl %edi
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; CHECK-NEXT: pushl %esi
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; CHECK-NEXT: subl $20, %esp
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
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; CHECK-NEXT: movl $8, %ecx
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; CHECK-NEXT: calll addfour@PLT
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; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)
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; CHECK-NEXT: movl $2, {{[0-9]+}}(%esp)
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; CHECK-NEXT: movl $1, {{[0-9]+}}(%esp)
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; CHECK-NEXT: calll foo@PLT
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; CHECK-NEXT: addl $20, %esp
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; CHECK-NEXT: popl %esi
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; CHECK-NEXT: popl %edi
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; CHECK-NEXT: popl %ebx
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; CHECK-NEXT: popl %ebp
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; CHECK-NEXT: retl
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entry:
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%0 = call cc 11 {i32, i32, i32} @addfour(i32 undef, i32 undef, i32 %a, i32 %b, i32 8)
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%res = extractvalue {i32, i32, i32} %0, 2
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tail call void @foo(i32 undef, i32 undef, i32 1, i32 2, i32 %res) nounwind
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ret void
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}
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define cc 11 {i32, i32, i32} @addfour(i32 %hp, i32 %p, i32 %x, i32 %y, i32 %z) nounwind {
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; CHECK-LABEL: addfour:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addl %edx, %eax
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; CHECK-NEXT: addl %ecx, %eax
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; CHECK-NEXT: retl
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entry:
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%0 = add i32 %x, %y
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%1 = add i32 %0, %z
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%res = insertvalue {i32, i32, i32} undef, i32 %1, 2
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ret {i32, i32, i32} %res
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}
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define cc 11 void @foo(i32 %hp, i32 %p, i32 %arg0, i32 %arg1, i32 %arg2) nounwind {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: subl $20, %esp
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; CHECK-NEXT: movl %esi, {{[0-9]+}}(%esp)
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; CHECK-NEXT: movl %ebp, {{[0-9]+}}(%esp)
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; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)
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; CHECK-NEXT: movl %edx, {{[0-9]+}}(%esp)
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; CHECK-NEXT: movl %ecx, (%esp)
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; CHECK-NEXT: addl $20, %esp
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; CHECK-NEXT: jmp bar@PLT # TAILCALL
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entry:
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%hp_var = alloca i32
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%p_var = alloca i32
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%arg0_var = alloca i32
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%arg1_var = alloca i32
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%arg2_var = alloca i32
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store i32 %hp, ptr %hp_var
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store i32 %p, ptr %p_var
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store i32 %arg0, ptr %arg0_var
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store i32 %arg1, ptr %arg1_var
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store i32 %arg2, ptr %arg2_var
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; These loads are loading the values from their previous stores and are optimized away.
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%0 = load i32, ptr %hp_var
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%1 = load i32, ptr %p_var
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%2 = load i32, ptr %arg0_var
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%3 = load i32, ptr %arg1_var
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%4 = load i32, ptr %arg2_var
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tail call cc 11 void @bar(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4) nounwind
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ret void
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}
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define cc 11 void @baz() nounwind {
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; CHECK-LABEL: baz:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl $42, %eax
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; CHECK-NEXT: jmpl *clos # TAILCALL
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%tmp_clos = load i32, ptr @clos
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%tmp_clos2 = inttoptr i32 %tmp_clos to ptr
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tail call cc 11 void %tmp_clos2(i32 undef, i32 undef, i32 42) nounwind
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ret void
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}
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; Sanity-check the tail call sequence. Number of arguments was chosen as to
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; expose a bug where the tail call sequence clobbered the stack.
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define cc 11 { i32, i32, i32 } @tailcaller(i32 %hp, i32 %p) nounwind {
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; CHECK-LABEL: tailcaller:
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; CHECK: # %bb.0:
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; CHECK-NEXT: subl $8, %esp
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)
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; CHECK-NEXT: movl $63, {{[0-9]+}}(%esp)
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; CHECK-NEXT: movl $15, %eax
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; CHECK-NEXT: movl $31, %edx
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; CHECK-NEXT: movl $47, %ecx
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; CHECK-NEXT: popl %edi
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; CHECK-NEXT: jmp tailcallee@PLT # TAILCALL
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%ret = tail call cc11 { i32, i32, i32 } @tailcallee(i32 %hp, i32 %p, i32 15,
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i32 31, i32 47, i32 63) nounwind
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ret { i32, i32, i32 } %ret
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}
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!hipe.literals = !{ !0, !1, !2 }
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!0 = !{ !"P_NSP_LIMIT", i32 84 }
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!1 = !{ !"X86_LEAF_WORDS", i32 24 }
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!2 = !{ !"AMD64_LEAF_WORDS", i32 24 }
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@clos = external dso_local constant i32
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declare cc 11 void @bar(i32, i32, i32, i32, i32)
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declare cc 11 { i32, i32, i32 } @tailcallee(i32, i32, i32, i32, i32, i32)
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!llvm.module.flags = !{!3}
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!3 = !{i32 2, !"override-stack-alignment", i32 4}
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