86eff6be68
This change adjusts the cost modeling used when the target does not have a schedule model with individual instruction latencies. After this change, we use the default latency information available from TargetSchedule. The default latency information essentially ends up treating most instructions as latency 1, with a few "expensive" ones getting a higher cost. Previously, we unconditionally applied the first legal pattern - without any consideration of profitability. As a result, this change both prevents some patterns being applied, and changes which patterns are exercised. (i.e. previously the first pattern was applied, afterwards, maybe the second one is because the first wasn't profitable.) The motivation here is two fold. First, this brings the default behavior in line with the behavior when -mcpu or -mtune is specified. This improves test coverage, and generally makes it less likely we will have bad surprises when providing more information to the compiler. Second, this enables some reassociation for ILP by default. Despite being unconditionally enabled, the prior code tended to "reassociate" repeatedly through an entire chain and simply moving the first operand to the end. The result was still a serial chain, just a different one. With this change, one of the intermediate transforms is unprofitable and we end up with a partially flattened tree. Note that the resulting code diffs show significant room for improvement in the basic algorithm. I am intentionally excluding those from this patch. For the test diffs, I don't seen any concerning regressions. I took a fairly close look at the RISCV ones, but only skimmed the x86 (particularly vector x86) changes. Differential Revision: https://reviews.llvm.org/D141017
136 lines
4.5 KiB
LLVM
136 lines
4.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -stack-symbol-ordering=0 -tailcallopt -relocation-model=static -code-model=medium -mtriple=x86_64-linux-gnu -mcpu=opteron | FileCheck %s
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; Check the HiPE calling convention works (x86-64)
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define void @zap(i64 %a, i64 %b) nounwind {
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; CHECK-LABEL: zap:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushq %rbp
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; CHECK-NEXT: pushq %r15
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; CHECK-NEXT: pushq %r14
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; CHECK-NEXT: pushq %r13
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; CHECK-NEXT: pushq %r12
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: movq %rsi, %rdx
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; CHECK-NEXT: movl $8, %ecx
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; CHECK-NEXT: movl $9, %r8d
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; CHECK-NEXT: movq %rdi, %rsi
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; CHECK-NEXT: callq addfour@PLT
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; CHECK-NEXT: movl $1, %edx
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; CHECK-NEXT: movl $2, %ecx
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; CHECK-NEXT: movl $3, %r8d
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; CHECK-NEXT: movq %rax, %r9
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; CHECK-NEXT: callq foo@PLT
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: popq %r12
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; CHECK-NEXT: popq %r13
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; CHECK-NEXT: popq %r14
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; CHECK-NEXT: popq %r15
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; CHECK-NEXT: popq %rbp
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; CHECK-NEXT: retq
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entry:
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%0 = call cc 11 {i64, i64, i64} @addfour(i64 undef, i64 undef, i64 %a, i64 %b, i64 8, i64 9)
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%res = extractvalue {i64, i64, i64} %0, 2
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tail call void @foo(i64 undef, i64 undef, i64 1, i64 2, i64 3, i64 %res) nounwind
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ret void
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}
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define cc 11 {i64, i64, i64} @addfour(i64 %hp, i64 %p, i64 %x, i64 %y, i64 %z, i64 %w) nounwind {
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; CHECK-LABEL: addfour:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addq %rsi, %rdx
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; CHECK-NEXT: leaq (%rcx,%r8), %rax
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; CHECK-NEXT: addq %rdx, %rax
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; CHECK-NEXT: retq
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entry:
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%0 = add i64 %x, %y
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%1 = add i64 %0, %z
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%2 = add i64 %1, %w
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%res = insertvalue {i64, i64, i64} undef, i64 %2, 2
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ret {i64, i64, i64} %res
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}
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define cc 11 void @foo(i64 %hp, i64 %p, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3) nounwind {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: subq $48, %rsp
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; CHECK-NEXT: movq %r15, {{[0-9]+}}(%rsp)
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; CHECK-NEXT: movq %rbp, {{[0-9]+}}(%rsp)
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; CHECK-NEXT: movq %rsi, {{[0-9]+}}(%rsp)
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; CHECK-NEXT: movq %rdx, {{[0-9]+}}(%rsp)
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; CHECK-NEXT: movq %rcx, {{[0-9]+}}(%rsp)
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; CHECK-NEXT: movq %r8, (%rsp)
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; CHECK-NEXT: addq $48, %rsp
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; CHECK-NEXT: jmp bar@PLT # TAILCALL
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entry:
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%hp_var = alloca i64
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%p_var = alloca i64
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%arg0_var = alloca i64
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%arg1_var = alloca i64
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%arg2_var = alloca i64
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%arg3_var = alloca i64
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store i64 %hp, ptr %hp_var
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store i64 %p, ptr %p_var
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store i64 %arg0, ptr %arg0_var
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store i64 %arg1, ptr %arg1_var
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store i64 %arg2, ptr %arg2_var
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store i64 %arg3, ptr %arg3_var
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; Loads are reading values just writen from corresponding register and are therefore noops.
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%0 = load i64, ptr %hp_var
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%1 = load i64, ptr %p_var
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%2 = load i64, ptr %arg0_var
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%3 = load i64, ptr %arg1_var
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%4 = load i64, ptr %arg2_var
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%5 = load i64, ptr %arg3_var
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tail call cc 11 void @bar(i64 %0, i64 %1, i64 %2, i64 %3, i64 %4, i64 %5) nounwind
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ret void
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}
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define cc 11 void @baz() nounwind {
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; CHECK-LABEL: baz:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq clos@GOTPCREL(%rip), %rax
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; CHECK-NEXT: movl $42, %esi
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; CHECK-NEXT: jmpq *(%rax) # TAILCALL
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%tmp_clos = load i64, ptr @clos
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%tmp_clos2 = inttoptr i64 %tmp_clos to ptr
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tail call cc 11 void %tmp_clos2(i64 undef, i64 undef, i64 42) nounwind
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ret void
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}
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; Sanity-check the tail call sequence. Number of arguments was chosen as to
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; expose a bug where the tail call sequence clobbered the stack.
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define cc 11 { i64, i64, i64 } @tailcaller(i64 %hp, i64 %p) #0 {
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; CHECK-LABEL: tailcaller:
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; CHECK: # %bb.0:
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; CHECK-NEXT: subq $16, %rsp
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
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; CHECK-NEXT: movq %rax, {{[0-9]+}}(%rsp)
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; CHECK-NEXT: movq $79, {{[0-9]+}}(%rsp)
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; CHECK-NEXT: movl $15, %esi
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; CHECK-NEXT: movl $31, %edx
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; CHECK-NEXT: movl $47, %ecx
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; CHECK-NEXT: movl $63, %r8d
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; CHECK-NEXT: popq %rax
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: jmp tailcallee@PLT # TAILCALL
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%ret = tail call cc11 { i64, i64, i64 } @tailcallee(i64 %hp, i64 %p, i64 15,
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i64 31, i64 47, i64 63, i64 79) #1
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ret { i64, i64, i64 } %ret
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}
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!hipe.literals = !{ !0, !1, !2 }
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!0 = !{ !"P_NSP_LIMIT", i32 160 }
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!1 = !{ !"X86_LEAF_WORDS", i32 24 }
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!2 = !{ !"AMD64_LEAF_WORDS", i32 24 }
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@clos = external constant i64
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declare cc 11 void @bar(i64, i64, i64, i64, i64, i64)
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declare cc 11 { i64, i64, i64 } @tailcallee(i64, i64, i64, i64, i64, i64, i64)
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!llvm.module.flags = !{!3}
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!3 = !{i32 2, !"override-stack-alignment", i32 8}
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