17eafe0841
If we lower a v2i64 shuffle to PSHUFD, we currently clamp undef elements to 0, (elements 0,1 of the v4i32) which can result in the shuffle referencing more elements of the source vector than expected, affecting later shuffle combines and KnownBits/SimplifyDemanded calls. By ensuring we widen the undef mask element we allow getV4X86ShuffleImm8 to use inline elements as the default, which are more likely to fold.
34 lines
1.3 KiB
LLVM
34 lines
1.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnux32 | FileCheck %s
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; RUN: not llc < %s -mtriple=i386-unknown-linux-gnu 2>&1 | FileCheck %s --check-prefix=ERROR
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; For 32-bit we still error since __int128 isn't supported in the frontend.
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; ERROR: error: couldn't allocate output register for constraint 'x'
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define { i64, i64 } @foo(i64 %0, i64 %1) {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq %rsi, %xmm0
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; CHECK-NEXT: movq %rdi, %xmm1
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; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
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; CHECK-NEXT: #APP
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; CHECK-NEXT: movdqa %xmm1, %xmm0
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: movq %xmm0, %rax
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; CHECK-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1,1]
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; CHECK-NEXT: movq %xmm0, %rdx
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; CHECK-NEXT: retq
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%3 = zext i64 %1 to i128
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%4 = shl nuw i128 %3, 64
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%5 = zext i64 %0 to i128
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%6 = or i128 %4, %5
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%7 = tail call i128 asm sideeffect "movdqa $1, $0", "=x,x,~{dirflag},~{fpsr},~{flags}"(i128 %6)
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%8 = trunc i128 %7 to i64
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%9 = lshr i128 %7, 64
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%10 = trunc i128 %9 to i64
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%11 = insertvalue { i64, i64 } undef, i64 %8, 0
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%12 = insertvalue { i64, i64 } %11, i64 %10, 1
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ret { i64, i64 } %12
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}
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