eece6ba283
AMDGPU has native instructions and target intrinsics for this, but these really should be subject to legalization and generic optimizations. This will enable legalization of f16->f32 on targets without f16 support. Implement a somewhat horrible inline expansion for targets without libcall support. This could be better if we could introduce control flow (GlobalISel version not yet implemented). Support for strictfp legalization is less complete but works for the simple cases.
78 lines
2.5 KiB
LLVM
78 lines
2.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
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; RUN: llc < %s -mtriple=i386-pc-win32 | FileCheck %s -check-prefix=CHECK-WIN
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define float @call_ldexpf(float %a, i32 %b) {
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; CHECK-LABEL: call_ldexpf:
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; CHECK: # %bb.0:
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; CHECK-NEXT: jmp ldexpf@PLT # TAILCALL
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;
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; CHECK-WIN-LABEL: call_ldexpf:
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; CHECK-WIN: # %bb.0:
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; CHECK-WIN-NEXT: subl $8, %esp
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; CHECK-WIN-NEXT: flds {{[0-9]+}}(%esp)
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; CHECK-WIN-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-WIN-NEXT: movl %eax, {{[0-9]+}}(%esp)
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; CHECK-WIN-NEXT: fstps (%esp)
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; CHECK-WIN-NEXT: calll _ldexpf
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; CHECK-WIN-NEXT: addl $8, %esp
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; CHECK-WIN-NEXT: retl
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%result = call float @ldexpf(float %a, i32 %b)
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ret float %result
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}
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define double @call_ldexp(double %a, i32 %b) {
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; CHECK-LABEL: call_ldexp:
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; CHECK: # %bb.0:
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; CHECK-NEXT: jmp ldexp@PLT # TAILCALL
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;
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; CHECK-WIN-LABEL: call_ldexp:
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; CHECK-WIN: # %bb.0:
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; CHECK-WIN-NEXT: subl $12, %esp
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; CHECK-WIN-NEXT: fldl {{[0-9]+}}(%esp)
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; CHECK-WIN-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-WIN-NEXT: movl %eax, {{[0-9]+}}(%esp)
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; CHECK-WIN-NEXT: fstpl (%esp)
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; CHECK-WIN-NEXT: calll _ldexp
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; CHECK-WIN-NEXT: addl $12, %esp
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; CHECK-WIN-NEXT: retl
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%result = call double @ldexp(double %a, i32 %b)
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ret double %result
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}
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define x86_fp80 @call_ldexpl(x86_fp80 %a, i32 %b) {
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; CHECK-LABEL: call_ldexpl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: subq $24, %rsp
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: fldt {{[0-9]+}}(%rsp)
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; CHECK-NEXT: fstpt (%rsp)
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; CHECK-NEXT: callq ldexpl@PLT
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; CHECK-NEXT: addq $24, %rsp
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: retq
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;
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; CHECK-WIN-LABEL: call_ldexpl:
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; CHECK-WIN: # %bb.0:
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; CHECK-WIN-NEXT: pushl %ebp
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; CHECK-WIN-NEXT: movl %esp, %ebp
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; CHECK-WIN-NEXT: andl $-16, %esp
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; CHECK-WIN-NEXT: subl $48, %esp
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; CHECK-WIN-NEXT: fldt 8(%ebp)
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; CHECK-WIN-NEXT: movl 24(%ebp), %eax
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; CHECK-WIN-NEXT: movl %eax, {{[0-9]+}}(%esp)
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; CHECK-WIN-NEXT: fstpt (%esp)
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; CHECK-WIN-NEXT: calll _ldexpl
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; CHECK-WIN-NEXT: movl %ebp, %esp
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; CHECK-WIN-NEXT: popl %ebp
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; CHECK-WIN-NEXT: retl
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%result = call x86_fp80 @ldexpl(x86_fp80 %a, i32 %b)
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ret x86_fp80 %result
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}
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declare float @ldexpf(float %a, i32 %b) #0
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declare double @ldexp(double %a, i32 %b) #0
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declare x86_fp80 @ldexpl(x86_fp80 %a, i32 %b) #0
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attributes #0 = { nounwind readonly }
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