Previously SelectionDAGBuilder used ABI alignment for compressstore/expandload. This patch allows SelectionDAGBuilder to use parameter alignment like vp intrinsics. This does not follow the original code to default use vector type alignment, since it is possible implemented to unaligned vector alignment.
46 lines
2.3 KiB
LLVM
46 lines
2.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -start-after=codegenprepare -stop-before finalize-isel | FileCheck %s
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define void @_Z3fooiPiPs(<8 x i32> %gepload, <8 x i1> %0) #0 {
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; CHECK-LABEL: name: _Z3fooiPiPs
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; CHECK: bb.0.entry:
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; CHECK-NEXT: liveins: $ymm0, $xmm1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY $xmm1
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr256x = COPY $ymm0
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; CHECK-NEXT: [[VPSLLWZ128ri:%[0-9]+]]:vr128x = VPSLLWZ128ri [[COPY]], 15
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; CHECK-NEXT: [[VPMOVW2MZ128rr:%[0-9]+]]:vk16wm = VPMOVW2MZ128rr killed [[VPSLLWZ128ri]]
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; CHECK-NEXT: [[VPMOVDWZ256rr:%[0-9]+]]:vr128x = VPMOVDWZ256rr [[COPY1]]
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; CHECK-NEXT: VPCOMPRESSWZ128mrk $noreg, 1, $noreg, 0, $noreg, killed [[VPMOVW2MZ128rr]], killed [[VPMOVDWZ256rr]] :: (store unknown-size into `ptr null`, align 1)
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; CHECK-NEXT: RET 0
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entry:
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%1 = trunc <8 x i32> %gepload to <8 x i16>
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tail call void @llvm.masked.compressstore.v8i16(<8 x i16> %1, ptr null, <8 x i1> %0)
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ret void
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}
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define void @_Z3foo2iPiPs(<8 x i32> %gepload, <8 x i1> %0) #0 {
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; CHECK-LABEL: name: _Z3foo2iPiPs
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; CHECK: bb.0.entry:
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; CHECK-NEXT: liveins: $ymm0, $xmm1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY $xmm1
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr256x = COPY $ymm0
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; CHECK-NEXT: [[VPSLLWZ128ri:%[0-9]+]]:vr128x = VPSLLWZ128ri [[COPY]], 15
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; CHECK-NEXT: [[VPMOVW2MZ128rr:%[0-9]+]]:vk16wm = VPMOVW2MZ128rr killed [[VPSLLWZ128ri]]
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; CHECK-NEXT: [[VPMOVDWZ256rr:%[0-9]+]]:vr128x = VPMOVDWZ256rr [[COPY1]]
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; CHECK-NEXT: VPCOMPRESSWZ128mrk $noreg, 1, $noreg, 0, $noreg, killed [[VPMOVW2MZ128rr]], killed [[VPMOVDWZ256rr]] :: (store unknown-size into `ptr null`, align 16)
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; CHECK-NEXT: RET 0
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entry:
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%1 = trunc <8 x i32> %gepload to <8 x i16>
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tail call void @llvm.masked.compressstore.v8i16(<8 x i16> %1, ptr align 16 null, <8 x i1> %0)
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ret void
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}
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; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
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declare void @llvm.masked.compressstore.v8i16(<8 x i16>, ptr nocapture, <8 x i1>) #1
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attributes #0 = { "target-cpu"="icelake-server" }
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attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
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