f0dd12ec5c
The first attempt missed changing test files for tools (update_llc_test_checks.py). Original commit message: This implements the main suggested change from issue #56498. Using the shorter (non-extending) instruction with only -Oz ("minsize") rather than -Os ("optsize") is left as a possible follow-up. As noted in the bug report, the zero-extending load may have shorter latency/better throughput across a wide range of x86 micro-arches, and it avoids a potential false dependency. The cost is an extra instruction byte. This could cause perf ups and downs from secondary effects, but I don't think it is possible to account for those in advance, and that will likely also depend on exact micro-arch. This does bring LLVM x86 codegen more in line with existing gcc codegen, so if problems are exposed they are more likely to occur for both compilers. Differential Revision: https://reviews.llvm.org/D129775
23 lines
669 B
LLVM
23 lines
669 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s --check-prefixes=X86
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; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefixes=X64
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define zeroext i1 @PR22473(ptr, i8) {
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; X86-LABEL: PR22473:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movzbl (%eax), %eax
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; X86-NEXT: cmpb {{[0-9]+}}(%esp), %al
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; X86-NEXT: sete %al
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; X86-NEXT: retl
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;
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; X64-LABEL: PR22473:
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; X64: # %bb.0:
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; X64-NEXT: cmpb %sil, (%rdi)
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; X64-NEXT: sete %al
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; X64-NEXT: retq
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%3 = load i8, ptr %0, align 1
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%4 = icmp eq i8 %3, %1
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ret i1 %4
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}
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