f0dd12ec5c
The first attempt missed changing test files for tools (update_llc_test_checks.py). Original commit message: This implements the main suggested change from issue #56498. Using the shorter (non-extending) instruction with only -Oz ("minsize") rather than -Os ("optsize") is left as a possible follow-up. As noted in the bug report, the zero-extending load may have shorter latency/better throughput across a wide range of x86 micro-arches, and it avoids a potential false dependency. The cost is an extra instruction byte. This could cause perf ups and downs from secondary effects, but I don't think it is possible to account for those in advance, and that will likely also depend on exact micro-arch. This does bring LLVM x86 codegen more in line with existing gcc codegen, so if problems are exposed they are more likely to occur for both compilers. Differential Revision: https://reviews.llvm.org/D129775
42 lines
1.4 KiB
LLVM
42 lines
1.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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;RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=slow-incdec | FileCheck %s
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@var_21 = external dso_local constant i32, align 4
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@var_29 = external dso_local constant i8, align 1
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@var_390 = external dso_local global i32, align 4
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@var_11 = external dso_local constant i8, align 1
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@var_370 = external dso_local global i8, align 1
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; Function Attrs: noinline nounwind optnone uwtable
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define void @_Z3foov() {
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; CHECK-LABEL: _Z3foov:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movsbl var_29(%rip), %eax
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; CHECK-NEXT: negl %eax
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; CHECK-NEXT: xorl %ecx, %ecx
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; CHECK-NEXT: cmpl %eax, var_21(%rip)
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; CHECK-NEXT: setb %cl
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; CHECK-NEXT: movl %ecx, var_390(%rip)
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; CHECK-NEXT: movzbl var_11(%rip), %eax
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; CHECK-NEXT: movb %al, var_370(%rip)
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; CHECK-NEXT: retq
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entry:
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%0 = load i32, ptr @var_21, align 4
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%1 = load i8, ptr @var_29, align 1
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%conv = sext i8 %1 to i32
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%sub = sub nsw i32 0, %conv
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%cmp = icmp ult i32 %0, %sub
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%conv1 = zext i1 %cmp to i32
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%add = add nsw i32 %conv1, -1
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%conv2 = trunc i32 %add to i8
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%tobool = icmp ne i8 %conv2, 0
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%lnot = xor i1 %tobool, true
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%conv3 = zext i1 %lnot to i32
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store i32 %conv3, ptr @var_390, align 4
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%2 = load i8, ptr @var_11, align 1
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%conv4 = sext i8 %2 to i16
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%conv5 = trunc i16 %conv4 to i8
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store i8 %conv5, ptr @var_370, align 1
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ret void
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}
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