f6ff2cc7e0
lowerBuildVectorAsBroadcast will not broadcast splat constants in all cases, resulting in a lot of situations where a full width vector load that has failed to fold but is loading splat constant values could use a broadcast load instruction just as cheaply, and save constant pool space. This is an updated commit ofab4b924832after being reverted at78de45fd4a
50 lines
1.9 KiB
LLVM
50 lines
1.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-- -mattr=avx512vl | FileCheck %s
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define <2 x i64> @undef_tval() {
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; CHECK-LABEL: undef_tval:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpbroadcastd {{.*#+}} xmm0 = [1,1,1,1,1,1,1,1]
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; CHECK-NEXT: movb $1, %al
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; CHECK-NEXT: kmovw %eax, %k1
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; CHECK-NEXT: vpmovqw %zmm0, %xmm0 {%k1}
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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%1 = tail call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64> undef, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, i8 1) #3
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%2 = bitcast <8 x i16> %1 to <2 x i64>
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ret <2 x i64> %2
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}
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define <2 x i64> @foo(<8 x i64> %x) {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpbroadcastd {{.*#+}} xmm1 = [1,1,1,1,1,1,1,1]
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; CHECK-NEXT: movb $1, %al
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; CHECK-NEXT: kmovw %eax, %k1
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; CHECK-NEXT: vpmovqw %zmm0, %xmm1 {%k1}
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; CHECK-NEXT: vmovdqa %xmm1, %xmm0
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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%1 = tail call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64> %x, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, i8 1) #3
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%2 = bitcast <8 x i16> %1 to <2 x i64>
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ret <2 x i64> %2
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}
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define <4 x i64> @goo(<16 x i32> %x) {
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; CHECK-LABEL: goo:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpbroadcastd {{.*#+}} ymm1 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
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; CHECK-NEXT: movw $1, %ax
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; CHECK-NEXT: kmovw %eax, %k1
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; CHECK-NEXT: vpmovdw %zmm0, %ymm1 {%k1}
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; CHECK-NEXT: vmovdqa %ymm1, %ymm0
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; CHECK-NEXT: retq
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%1 = tail call <16 x i16> @llvm.x86.avx512.mask.pmov.dw.512(<16 x i32> %x, <16 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, i16 1) #3
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%2 = bitcast <16 x i16> %1 to <4 x i64>
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ret <4 x i64> %2
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}
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declare <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64>, <8 x i16>, i8)
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declare <16 x i16> @llvm.x86.avx512.mask.pmov.dw.512(<16 x i32>, <16 x i16>, i16)
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