189900eb14
This stops reporting CostPerUse 1 for `R8`-`R15` and `XMM8`-`XMM31`.
This was previously done because instruction encoding require a REX
prefix when using them resulting in longer instruction encodings. I
found that this regresses the quality of the register allocation as the
costs impose an ordering on eviction candidates. I also feel that there
is a bit of an impedance mismatch as the actual costs occure when
encoding instructions using those registers, but the order of VReg
assignments is not primarily ordered by number of Defs+Uses.
I did extensive measurements with the llvm-test-suite wiht SPEC2006 +
SPEC2017 included, internal services showed similar patterns. Generally
there are a log of improvements but also a lot of regression. But on
average the allocation quality seems to improve at a small code size
regression.
Results for measuring static and dynamic instruction counts:
Dynamic Counts (scaled by execution frequency) / Optimization Remarks:
Spills+FoldedSpills -5.6%
Reloads+FoldedReloads -4.2%
Copies -0.1%
Static / LLVM Statistics:
regalloc.NumSpills mean -1.6%, geomean -2.8%
regalloc.NumReloads mean -1.7%, geomean -3.1%
size..text mean +0.4%, geomean +0.4%
Static / LLVM Statistics:
mean -2.2%, geomean -3.1%) regalloc.NumSpills
mean -2.6%, geomean -3.9%) regalloc.NumReloads
mean +0.6%, geomean +0.6%) size..text
Static / LLVM Statistics:
regalloc.NumSpills mean -3.0%
regalloc.NumReloads mean -3.3%
size..text mean +0.3%, geomean +0.3%
Differential Revision: https://reviews.llvm.org/D133902
66 lines
2.7 KiB
LLVM
66 lines
2.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O3 -mtriple=x86_64-linux-generic -mattr=avx < %s | FileCheck %s
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; Bug 45563:
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; The LowerMLOAD() method AVX masked load branch should
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; use the operand vector type rather than the mask type.
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; Given, for example:
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; v4f64,ch = masked_load ..
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; The select should be:
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; v4f64 = vselect ..
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; instead of:
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; v4i64 = vselect ..
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define <16 x double> @bug45563(ptr %addr, <16 x double> %dst, <16 x i64> %e, <16 x i64> %f) {
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; CHECK-LABEL: bug45563:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pushq %rbp
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset %rbp, -16
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; CHECK-NEXT: movq %rsp, %rbp
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; CHECK-NEXT: .cfi_def_cfa_register %rbp
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; CHECK-NEXT: andq $-32, %rsp
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; CHECK-NEXT: subq $32, %rsp
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; CHECK-NEXT: vextractf128 $1, %ymm7, %xmm8
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; CHECK-NEXT: vmovdqa 112(%rbp), %xmm9
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; CHECK-NEXT: vmovdqa 128(%rbp), %xmm10
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; CHECK-NEXT: vpcmpgtq %xmm8, %xmm10, %xmm8
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; CHECK-NEXT: vpcmpgtq %xmm7, %xmm9, %xmm7
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; CHECK-NEXT: vinsertf128 $1, %xmm8, %ymm7, %ymm7
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; CHECK-NEXT: vextractf128 $1, %ymm6, %xmm8
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; CHECK-NEXT: vmovdqa 80(%rbp), %xmm9
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; CHECK-NEXT: vmovdqa 96(%rbp), %xmm10
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; CHECK-NEXT: vpcmpgtq %xmm8, %xmm10, %xmm8
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; CHECK-NEXT: vpcmpgtq %xmm6, %xmm9, %xmm6
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; CHECK-NEXT: vinsertf128 $1, %xmm8, %ymm6, %ymm6
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; CHECK-NEXT: vextractf128 $1, %ymm5, %xmm8
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; CHECK-NEXT: vmovdqa 48(%rbp), %xmm9
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; CHECK-NEXT: vmovdqa 64(%rbp), %xmm10
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; CHECK-NEXT: vpcmpgtq %xmm8, %xmm10, %xmm8
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; CHECK-NEXT: vpcmpgtq %xmm5, %xmm9, %xmm5
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; CHECK-NEXT: vinsertf128 $1, %xmm8, %ymm5, %ymm5
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; CHECK-NEXT: vextractf128 $1, %ymm4, %xmm8
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; CHECK-NEXT: vmovdqa 16(%rbp), %xmm9
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; CHECK-NEXT: vmovdqa 32(%rbp), %xmm10
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; CHECK-NEXT: vpcmpgtq %xmm8, %xmm10, %xmm8
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; CHECK-NEXT: vpcmpgtq %xmm4, %xmm9, %xmm4
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; CHECK-NEXT: vinsertf128 $1, %xmm8, %ymm4, %ymm4
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; CHECK-NEXT: vmaskmovpd (%rdi), %ymm4, %ymm8
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; CHECK-NEXT: vblendvpd %ymm4, %ymm8, %ymm0, %ymm0
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; CHECK-NEXT: vmaskmovpd 32(%rdi), %ymm5, %ymm4
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; CHECK-NEXT: vblendvpd %ymm5, %ymm4, %ymm1, %ymm1
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; CHECK-NEXT: vmaskmovpd 64(%rdi), %ymm6, %ymm4
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; CHECK-NEXT: vblendvpd %ymm6, %ymm4, %ymm2, %ymm2
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; CHECK-NEXT: vmaskmovpd 96(%rdi), %ymm7, %ymm4
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; CHECK-NEXT: vblendvpd %ymm7, %ymm4, %ymm3, %ymm3
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; CHECK-NEXT: movq %rbp, %rsp
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; CHECK-NEXT: popq %rbp
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; CHECK-NEXT: .cfi_def_cfa %rsp, 8
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; CHECK-NEXT: retq
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%mask = icmp slt <16 x i64> %e, %f
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%res = call <16 x double> @llvm.masked.load.v16f64.p0(ptr %addr, i32 4, <16 x i1>%mask, <16 x double> %dst)
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ret <16 x double> %res
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}
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declare <16 x double> @llvm.masked.load.v16f64.p0(ptr %addr, i32 %align, <16 x i1> %mask, <16 x double> %dst)
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