f0dd12ec5c
The first attempt missed changing test files for tools (update_llc_test_checks.py). Original commit message: This implements the main suggested change from issue #56498. Using the shorter (non-extending) instruction with only -Oz ("minsize") rather than -Os ("optsize") is left as a possible follow-up. As noted in the bug report, the zero-extending load may have shorter latency/better throughput across a wide range of x86 micro-arches, and it avoids a potential false dependency. The cost is an extra instruction byte. This could cause perf ups and downs from secondary effects, but I don't think it is possible to account for those in advance, and that will likely also depend on exact micro-arch. This does bring LLVM x86 codegen more in line with existing gcc codegen, so if problems are exposed they are more likely to occur for both compilers. Differential Revision: https://reviews.llvm.org/D129775
35 lines
1.1 KiB
LLVM
35 lines
1.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-- -x86-asm-syntax=intel | FileCheck %s
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; PR687
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define i64 @foo(i64 %x, ptr %X) {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0:
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; CHECK-NEXT: push esi
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: .cfi_offset esi, -8
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; CHECK-NEXT: mov esi, dword ptr [esp + 8]
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; CHECK-NEXT: mov edx, dword ptr [esp + 12]
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; CHECK-NEXT: mov eax, dword ptr [esp + 16]
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; CHECK-NEXT: movzx ecx, byte ptr [eax]
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; CHECK-NEXT: mov eax, esi
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; CHECK-NEXT: shl eax, cl
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; CHECK-NEXT: shld edx, esi, cl
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; CHECK-NEXT: test cl, 32
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; CHECK-NEXT: je .LBB0_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: mov edx, eax
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; CHECK-NEXT: xor eax, eax
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; CHECK-NEXT: .LBB0_2:
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; CHECK-NEXT: pop esi
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; CHECK-NEXT: .cfi_def_cfa_offset 4
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; CHECK-NEXT: ret
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%tmp.1 = load i64, ptr %X ; <i64> [#uses=1]
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%tmp.3 = trunc i64 %tmp.1 to i8 ; <i8> [#uses=1]
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%shift.upgrd.1 = zext i8 %tmp.3 to i64 ; <i64> [#uses=1]
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%tmp.4 = shl i64 %x, %shift.upgrd.1 ; <i64> [#uses=1]
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ret i64 %tmp.4
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}
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