ee5585ed09
Improve and enable folding of conditional branches with tail calls. 1. Make it so that conditional tail calls can be emitted even when there are multiple predecessors. 2. Don't guard the transformation behind -Os. The rationale for guarding it was static-prediction can be affected by whether the branch is forward of backward. This is no longer true for almost any X86 cpus (anything newer than `SnB`) so is no longer a meaningful concern. Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D140931
183 lines
4.9 KiB
LLVM
183 lines
4.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=i386-unknown-linux-gnu -mattr=-slow-incdec < %s | FileCheck -check-prefix=CHECK -check-prefix=INCDEC %s
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; RUN: llc -mtriple=i386-unknown-linux-gnu -mattr=+slow-incdec < %s | FileCheck -check-prefix=CHECK -check-prefix=ADD %s
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define i32 @inc(i32 %x) {
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; INCDEC-LABEL: inc:
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; INCDEC: # %bb.0:
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; INCDEC-NEXT: movl {{[0-9]+}}(%esp), %eax
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; INCDEC-NEXT: incl %eax
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; INCDEC-NEXT: retl
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;
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; ADD-LABEL: inc:
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; ADD: # %bb.0:
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; ADD-NEXT: movl {{[0-9]+}}(%esp), %eax
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; ADD-NEXT: addl $1, %eax
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; ADD-NEXT: retl
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%r = add i32 %x, 1
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ret i32 %r
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}
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define i32 @dec(i32 %x) {
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; INCDEC-LABEL: dec:
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; INCDEC: # %bb.0:
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; INCDEC-NEXT: movl {{[0-9]+}}(%esp), %eax
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; INCDEC-NEXT: decl %eax
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; INCDEC-NEXT: retl
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;
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; ADD-LABEL: dec:
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; ADD: # %bb.0:
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; ADD-NEXT: movl {{[0-9]+}}(%esp), %eax
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; ADD-NEXT: addl $-1, %eax
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; ADD-NEXT: retl
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%r = add i32 %x, -1
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ret i32 %r
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}
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define i32 @inc_size(i32 %x) optsize {
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; CHECK-LABEL: inc_size:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: incl %eax
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; CHECK-NEXT: retl
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%r = add i32 %x, 1
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ret i32 %r
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}
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define i32 @dec_size(i32 %x) optsize {
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; CHECK-LABEL: dec_size:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: decl %eax
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; CHECK-NEXT: retl
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%r = add i32 %x, -1
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ret i32 %r
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}
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define i32 @inc_pgso(i32 %x) !prof !14 {
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; CHECK-LABEL: inc_pgso:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: incl %eax
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; CHECK-NEXT: retl
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%r = add i32 %x, 1
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ret i32 %r
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}
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define i32 @dec_pgso(i32 %x) !prof !14 {
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; CHECK-LABEL: dec_pgso:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: decl %eax
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; CHECK-NEXT: retl
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%r = add i32 %x, -1
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ret i32 %r
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}
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declare {i32, i1} @llvm.uadd.with.overflow.i32(i32, i32)
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declare void @other(ptr ) nounwind;
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define void @cond_ae_to_cond_ne(ptr %p) nounwind {
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; INCDEC-LABEL: cond_ae_to_cond_ne:
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; INCDEC: # %bb.0: # %entry
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; INCDEC-NEXT: movl {{[0-9]+}}(%esp), %eax
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; INCDEC-NEXT: incl (%eax)
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; INCDEC-NEXT: je other@PLT # TAILCALL
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; INCDEC-NEXT: # %bb.1: # %return
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; INCDEC-NEXT: retl
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;
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; ADD-LABEL: cond_ae_to_cond_ne:
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; ADD: # %bb.0: # %entry
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; ADD-NEXT: movl {{[0-9]+}}(%esp), %eax
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; ADD-NEXT: addl $1, (%eax)
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; ADD-NEXT: je other@PLT # TAILCALL
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; ADD-NEXT: # %bb.1: # %return
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; ADD-NEXT: retl
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entry:
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%t0 = load i32, ptr %p, align 8
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%add_ov = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %t0, i32 1)
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%inc = extractvalue { i32, i1 } %add_ov, 0
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store i32 %inc, ptr %p, align 8
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%ov = extractvalue { i32, i1 } %add_ov, 1
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br i1 %ov, label %if.end4, label %return
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if.end4:
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tail call void @other(ptr %p) nounwind
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br label %return
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return:
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ret void
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}
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@a = common global i8 0, align 1
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@d = common global i8 0, align 1
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declare void @external_a()
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declare void @external_b()
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declare {i8, i1} @llvm.uadd.with.overflow.i8(i8, i8)
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define void @test_tail_call(ptr %ptr) nounwind {
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; INCDEC-LABEL: test_tail_call:
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; INCDEC: # %bb.0: # %entry
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; INCDEC-NEXT: movl {{[0-9]+}}(%esp), %eax
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; INCDEC-NEXT: incl (%eax)
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; INCDEC-NEXT: setne %al
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; INCDEC-NEXT: incb a
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; INCDEC-NEXT: sete d
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; INCDEC-NEXT: testb %al, %al
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; INCDEC-NEXT: jne external_b@PLT # TAILCALL
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; INCDEC-NEXT: # %bb.1: # %then
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; INCDEC-NEXT: jmp external_a@PLT # TAILCALL
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;
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; ADD-LABEL: test_tail_call:
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; ADD: # %bb.0: # %entry
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; ADD-NEXT: movl {{[0-9]+}}(%esp), %eax
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; ADD-NEXT: addl $1, (%eax)
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; ADD-NEXT: setne %al
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; ADD-NEXT: addb $1, a
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; ADD-NEXT: sete d
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; ADD-NEXT: testb %al, %al
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; ADD-NEXT: jne external_b@PLT # TAILCALL
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; ADD-NEXT: # %bb.1: # %then
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; ADD-NEXT: jmp external_a@PLT # TAILCALL
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entry:
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%val = load i32, ptr %ptr
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%add_ov = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %val, i32 1)
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%inc = extractvalue { i32, i1 } %add_ov, 0
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store i32 %inc, ptr %ptr
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%cmp = extractvalue { i32, i1 } %add_ov, 1
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%aval = load volatile i8, ptr @a
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%add_ov2 = call {i8, i1} @llvm.uadd.with.overflow.i8(i8 %aval, i8 1)
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%inc2 = extractvalue { i8, i1 } %add_ov2, 0
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store volatile i8 %inc2, ptr @a
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%cmp2 = extractvalue { i8, i1 } %add_ov2, 1
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%conv5 = zext i1 %cmp2 to i8
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store i8 %conv5, ptr @d
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br i1 %cmp, label %then, label %else
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then:
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tail call void @external_a()
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ret void
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else:
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tail call void @external_b()
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ret void
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}
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!llvm.module.flags = !{!0}
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!0 = !{i32 1, !"ProfileSummary", !1}
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!1 = !{!2, !3, !4, !5, !6, !7, !8, !9}
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!2 = !{!"ProfileFormat", !"InstrProf"}
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!3 = !{!"TotalCount", i64 10000}
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!4 = !{!"MaxCount", i64 10}
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!5 = !{!"MaxInternalCount", i64 1}
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!6 = !{!"MaxFunctionCount", i64 1000}
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!7 = !{!"NumCounts", i64 3}
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!8 = !{!"NumFunctions", i64 3}
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!9 = !{!"DetailedSummary", !10}
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!10 = !{!11, !12, !13}
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!11 = !{i32 10000, i64 100, i32 1}
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!12 = !{i32 999000, i64 100, i32 1}
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!13 = !{i32 999999, i64 1, i32 2}
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!14 = !{!"function_entry_count", i64 0}
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